Formation of structure to accurately measure source/drain...

Details Formation of structure to accurately measure source/drain... Formation of structure to accurately measure source/drain...

2000-02-02

2001-08-14

Utech, Benjamin L. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S719000, C438S723000, C438S733000, C438S743000, C438S745000

Reexamination Certificate

active

06274501

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of forming an electrical contact on a semiconductor substrate. The invention has particular applicability in testing electrical characteristics of active regions of semiconductor devices.
BACKGROUND ART
Current demands for high density and performance associated with ultra large scale integration require submicron features of about 0.18 microns and under, increased transistor and circuit speeds and improved reliability. Such demands for increased density, performance and reliability require formation of device features with high precision and uniformity. Consequently, the need for device optimization, including accurate measuring of device electrical characteristics, has become increasingly critical.
Metal oxide semiconductor (MOS) devices, as depicted in
FIG. 1
, are the building blocks of today's circuits, and typically comprise a pair of active regions
110
(also called source/drain regions) formed, as by ion implantation, in a silicon substrate
100
, and separated by an ion-implanted channel region
120
. A gate oxide layer
130
is formed above channel region
120
, and a conductive gate
140
, such as a polysilicon gate, is formed on gate oxide layer
130
.
To predict device performance, circuit designers typically employ “compact models” in the form of software, which characterize transistors, such as MOS devices, using a limited number of measured device electrical characteristics. The results of compact modeling are then used in circuit simulation to optimize the circuit. An important input for compact modeling is source/drain resistance; that is, the resistance carriers meet when they move from a source/drain region
110
to channel region
120
. It is highly desirable to obtain an accurate measurement of source/drain resistance (Rds). However, Rds of an actual device cannot be measured directly using conventional techniques. Rather, the prior art typically derives Rds after measuring other electrical characteristics; e.g., the drain current of devices at different gate voltages.
One such prior art technique is illustrated in
FIG. 2
, wherein Rds is derived by comparing voltage and current measurements of a “nominal” device to those of a long channel device. As shown in
FIG. 2
, which graphs gate length along the x-axis and Rds along the y-axis, a particular gate voltage Vg′ is selected, and the corresponding drain current IVg′ is measured for different gate lengths, enabling calculation of Rds at each gate length to produce a line, as shown. Then, a different gate voltage Vg″ is selected and the procedure repeated. In theory, the y-coordinate of the point where the lines associated with Ivg′ and Ivg″ cross is the desired value of RDS of a nominal device.
This technique produces an acceptably accurate value of Rds when the channel region of the device is uniformly doped. Disadvantageously, as device structures become more complex and channel regions are non-uniformly doped to optimize device performance (e.g., using retrograded doping profiles, pocket implants, HALO implants, etc.), the validity of such conventional techniques for deriving Rds no longer holds, and it becomes much more difficult to derive accurate Rds values.
There exists a need for a methodology for accurately measuring Rds of MOS devices directly, thereby enabling more accurate compact modeling of such devices and, consequently, facilitating device optimization.
SUMMARY OF THE INVENTION
An advantage of the present invention is a method of directly and accurately measuring source/drain resistance of a MOS device.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method for forming an electrical contact on a main surface of a semiconductor substrate to an active region in the substrate, wherein a gate oxide layer is disposed on a portion of the active region and extends over an edge of the active region, a gate is disposed on the gate oxide layer, and a sidewall spacer of a dielectric material is disposed on a sidewall of the gate and extends onto the active region. The method comprises etching to remove the gate and the gate oxide layer; forming a sacrificial oxide layer on the sidewall spacer and the main surface; anisotropically etching the sacrificial oxide layer to form a sacrificial oxide spacer on the sidewall spacer and extending onto the main surface; forming a layer of the dielectric material on the sacrificial oxide spacer and extending onto the main surface; selectively etching to remove the sacrificial oxide spacer and expose a portion of the main surface while preserving the sidewall spacer and dielectric material layer; and forming a metal layer on the exposed portion of the main surface between the sidewall spacer and the dielectric material layer to form the electrical contact.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.


REFERENCES:
patent: 5869879 (1999-02-01), Fulford, Jr. et al.
patent: 6005272 (1999-12-01), Gardner et al.
patent: 6110790 (2000-08-01), Chen
patent: 6127232 (2000-10-01), Chatterjee
patent: 6140219 (2000-10-01), Dennison

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