Formation of self-aligned stacked CMOS structures by lift-off

Details Formation of self-aligned stacked CMOS structures by lift-off Formation of self-aligned stacked CMOS structures by lift-off

1986-08-11

1987-07-14

Hearn, Brian E.

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29576J, 29578, 148 15, 148187, 148DIG164, 357 237, 357 41, 357 45, 357 59, 357 91, H01L 2978, H01L 2904, H01L 2702

Patent

active

046792996

ABSTRACT:
A process for fabricating a self-aligned three-dimensionally integrated circuit structure having two channel regions responsive to a common gate electrode. A relatively thick lift-off region is formed over and in alignment with the gate electrode. A thick oxide layer is then deposited over the structure so as to form stressed oxide extending from the lift-off layer sidewalls. A selective etch of the stressed oxide follows. The relatively thick oxide covering the lift-off layer is then removed with the etch of the lift-off layer, the lift-off etch acting through the exposed lift-off layer sidewalls. The formation of an upper field effect transistor gate oxide and a conformal deposition of polysilicon for the channel and source/drain regions follows. The conformally deposited polysilicon retains the contour of the recess formed by the lift-off. The gate aligned recess is then filled with a dopant masking material by deposition and etching, which dopant masking material thereafter defines during implant or diffusion an upper field effect transistor channel region self-aligned with the common gate electrode. The characteristics of the upper field effect transistor can be improved by applying laser recrystallization techniques.

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