Formation of low resistance via contacts in interconnect...

Details Formation of low resistance via contacts in interconnect... Formation of low resistance via contacts in interconnect...

2005-07-15

2008-05-27

Pham, Thanhha (Department: 2813)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S700000, C257SE21579

Reexamination Certificate

active

07378350

ABSTRACT:
A method of fabricating BEOL interconnect structures on a semiconductor device having a plurality of via contacts with low via contact resistance is provided. The method includes the steps of: a) forming a porous or dense low k dielectric layer on a substrate; b) forming single or dual damascene etched openings in the low k dielectric; c) placing the substrate in a process chamber on a cold chuck at a temperature about −200° C. to about 25° C.; d) adding to the process chamber a condensable cleaning agent (CCA) to condense a layer of CCA within the etched openings on the substrate; and e) performing an activation step while the wafer remains cold at a temperature of about −200° C. to about 25° C. The via contacts are very stable during thermal cycles and during operation of the semiconductor device.

REFERENCES:
patent: 4884123 (1989-11-01), Dixit et al.
patent: 6312793 (2001-11-01), Grill et al.
patent: 6337277 (2002-01-01), Chou et al.
patent: 6358832 (2002-03-01), Edelstein et al.
patent: 6441491 (2002-08-01), Grill et al.
patent: 6479110 (2002-11-01), Grill et al.
patent: 6848455 (2005-02-01), Shrinivasan et al.
patent: 2001/0045651 (2001-11-01), Saito et al.

Affiliated with

Also associated with

Rating

Formation of low resistance via contacts in interconnect... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Formation of low resistance via contacts in interconnect..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Formation of low resistance via contacts in interconnect... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3982757