Formation of lattice-tuning semiconductor substrates

Details Formation of lattice-tuning semiconductor substrates Formation of lattice-tuning semiconductor substrates

2007-02-20

2007-02-20

Smith, Zandra V. (Department: 2822)

Semiconductor device manufacturing: process

Formation of semiconductive active region on any substrate

Polycrystalline semiconductor

C438S488000, C438S489000, C438S492000, C438S493000, C438S496000, C438S602000, C438S603000, C438S604000, C438S933000

Reexamination Certificate

active

10525987

ABSTRACT:
A method of forming a lattice-tuning semiconductor substrate comprises the steps of defining parallel strips of a Si surface by the provision of spaced parallel oxide walls (2) on the surface, selectively growing a first SiGe layer on the strips such that first dislocations (3) extend preferentially across the first SiGe layer between the walls (2) to relieve the strain in the first SiGe layer in directions transverse to the walls (2), and growing a second SiGe layer on top of the first SiGe layer to overgrow the walls (2) such that second dislocations form preferentially within the second SiGe layer above the walls (2) to relieve the strain in the second SiGe layer in directions transverse to the first dislocations (3). The dislocations so produced serve to relax the material in two mutually transverse directions whilst being spatially separated so that the two sets of dislocations cannot interact with one another. Thus the density of threading dislocations and the surface roughness is greatly reduced, thus enhancing the performance of the virtual substrate by decreasing the disruption of the atomic lattice that can lead to scattering of electrons in the active devices and degradation of the speed of movement of the electrons.

REFERENCES:
patent: 5108947 (1992-04-01), Demeester et al.
patent: 5158907 (1992-10-01), Fitzgerald, Jr.
patent: 5238869 (1993-08-01), Shichijo et al.
patent: 5272105 (1993-12-01), Yacobi et al.
patent: 5410167 (1995-04-01), Saito
patent: 5442205 (1995-08-01), Brasen et al.
patent: 2002/0017642 (2002-02-01), Mizushima et al.
patent: 1 052 684 (2000-11-01), None
patent: 2 215 514 (1989-09-01), None
patent: WO 99/14804 (1999-03-01), None
patent: WO 99/38201 (1999-07-01), None
patent: WO 01/01465 (2001-01-01), None
“Molecular beam epitaxy of strained Si1-xGexlayers on patterned substrates” Jun. 1, 1993, Journal of Crystal Growth, North-Holland Publishing Co., vol. 130, Nos. 3/4, pp. 611-616, Bugiel et al.

Affiliated with

Also associated with

Rating

Formation of lattice-tuning semiconductor substrates does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Formation of lattice-tuning semiconductor substrates, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Formation of lattice-tuning semiconductor substrates will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3839471