Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2000-02-24
2001-06-26
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S231000, C438S232000, C438S305000, C438S306000, C438S514000, C438S516000, C438S664000, C438S530000, C438S532000
Reexamination Certificate
active
06251757
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to a method for fabricating a highly activated shallow abrupt junction for the drain and the source extensions of a field effect transistor by thermal budget engineering.
BACKGROUND OF THE INVENTION
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to
FIG. 1
, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
which is fabricated within a semiconductor substrate
102
. The scaled down MOSFET
100
having submicron or nanometer dimensions includes a drain extension
104
and a source extension
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension
104
and the source extension
106
are shallow junctions to minimize short-channel effects in the MOSFET
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET
100
further includes a drain contact junction
108
with a drain silicide
110
for providing contact to the drain of the MOSFET
100
and includes a source contact junction
112
with a source silicide
114
for providing contact to the source of the MOSFET
100
. The drain contact junction
108
and the source contact junction
112
are fabricated as deeper junctions such that a relatively large size of the drain silicide
110
and the source silicide
114
respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET
100
.
The MOSFET
100
further includes a gate dielectric
116
and a gate structure
118
which may be a polysilicon gate. A gate silicide
120
is formed on the polysilicon gate
118
for providing contact to the polysilicon gate
118
. The MOSFET
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
, within the semiconductor substrate
102
, where a MOSFET is fabricated therein.
The MOSFET
100
also includes a spacer
122
disposed on the sidewalls of the polysilicon gate
118
and the gate oxide
116
. When the spacer
122
is comprised of silicon nitride (SiN), then a spacer liner oxide
124
is deposited as a buffer layer between the spacer
122
and the sidewalls of the polysilicon gate
118
and the gate oxide
116
.
As dimensions of the MOSFET
100
are scaled further down to tens of nanometers, the drain extension
104
and the source extension
106
are desired to be abrupt and shallow junctions to minimize short-channel effects of the MOSFET
100
, as known to one of ordinary skill in the art of integrated circuit fabrication. In addition, for enhancing the speed performance of the MOSFET
100
with scaled down dimensions, a high dopant concentration with high activation in the drain extension
104
and the source extension
106
is desired.
In the prior art, dopant within the drain extension
104
and the source extension
106
are activated using an activation RTA (Rapid Thermal Anneal) process. In addition, the silicides
110
,
114
,
120
are formed with an additional silicidation RTA (Rapid Thermal Anneal) process. The additional silicidation RTA process further heats up the semiconductor wafer
102
, and such additional heating may deactivate the dopant within the drain extension
104
and the source extension
106
that have already been fully activated, as known to one of ordinary skill in the art of integrated circuit fabrication.
Such deactivation of the dopant within the drain extension
104
and the source extension
106
decreases the carrier mobility within the drain extension
104
and the source extension
106
and increases the series resistance at the drain and the source of the MOSFET
100
. Such increase in series resistance at the drain and the source of the MOSFET
100
degrades the speed performance of the MOSFET
100
.
However, the silicidation RTA (Rapid Thermal Anneal) process is desired for forming the silicides
110
,
114
, and
120
of the MOSFET
100
. Thus, a method is desired for forming highly activated shallow abrupt junctions for the drain extension
110
and the source extension
114
of the MOSFET
100
despite the silicidation RTA (Rapid Thermal Anneal) process.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, highly activated shallow abrupt junctions are formed in a semiconductor substrate given the performance of the silicidation RTA (Rapid Thermal Anneal), by thermal budget engineering.
In one embodiment of the present invention, in a method for fabricating a highly activated shallow abrupt doped junction in a semiconductor substrate, a first dopant is implanted into a predetermined surface of the semiconductor substrate to form a preamorphization junction having a first predetermined depth from the predetermined surface of the semiconductor substrate. Furthermore, a second dopant is implanted into the preamorphization junction with a dopant profile along a depth of the semiconductor substrate from the predetermined surface of the semiconductor substrate. A peak of the dopant profile is located at a fraction of the first predetermined depth of the preamorphization junction. A silicidation RTA (Rapid Thermal Anneal) is performed to form silicide on the semiconductor substrate. The silicidation RTA (Rapid Thermal Anneal) recrystallizes the preamorphization junction from the first predetermined depth of the preamorphization junction up to an unrecrystallized depth of the preamorphization junction. The unrecrystallized depth of the preamorphization junction does not reach up to the peak of the dopant profile.
An additional RTA (Rapid Thermal Anneal) is performed to recrystallize the preamorphization junction from the unrecrystallized depth of the preamorphization junction substantially up to the predetermined surface of the semiconductor substrate. The highly activated shallow abrupt doped junction is formed by activation of a substantial portion of the second dopant in the preamorphization junction during the additional RTA (Rapid Thermal Anneal).
In this manner, because the preamorphization junction is relatively deeper than the peak concentration of the second dopant, the silicidation RTA (Rapid Thermal Anneal) process recrystallizes only a portion of the preamorphization junction. Thus, the additional RTA (Rapid Thermal Anneal) process recrystallizes the portion of the preamorphization junction having a substantial portion of the second dopant such that deactivation of the second dopant is minimized. With such minimization of the deactivation of the second dopant, when the highly activated shallow abrupt doped junction is a drain or a source of a MOSFET (Metal Oxide Field Effect Transistor), the series resistance at the drain and the source of the MOSFET is minimized to enhance the speed performance of the MOSFET.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.
REFERENCES:
patent: 5266510 (1993-11-01), Lee
patent: 6037204 (2000-03-01), Chang et al.
Advanced Micro Devices , Inc.
Choi Monica H.
Lytle Craig P.
Smith Matthew
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