Formation of high-k gate dielectric layers for MOS devices...

Details Formation of high-k gate dielectric layers for MOS devices... Formation of high-k gate dielectric layers for MOS devices...

2002-05-16

2004-08-31

Fahmy, Wael (Department: 2814)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S197000, C438S198000, C438S199000

Reexamination Certificate

active

06784101

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the manufacture of high speed, high performance MOS semiconductor devices fabricated on strained lattice semiconductor substrates, and MOS devices obtained thereby. Specifically, the present invention relates to an improved method of manufacturing MOS devices including gate insulator layers comprised of high-k dielectric materials on strained lattice semiconductor substrates, which method substantially eliminates, or at least minimizes, stress relaxation of the strained lattice semiconductor layer attendant upon gate insulator layer formation.
BACKGROUND OF THE INVENTION
Recently, there has been much interest in investigating the feasibility of various approaches having the aim or goal of developing new semiconductor materials which provide increased speeds of electron and hole flow therethrough, thereby permitting fabrication of semiconductor devices, such as integrated circuit (IC) devices, with higher operating speeds, enhanced performance characteristics, and lower power consumption. One such material which shows promise in attaining the goal of higher device operating speeds is termed “strained silicon”.
According to this approach, a very thin, tensilely strained, crystalline silicon (Si) layer is grown on a relaxed, graded composition Si—Ge buffer layer several microns thick, which Si—Ge buffer layer is, in turn, formed on a suitable crystalline substrate, e.g., a Si wafer or a silicon-on-insulator (SOI) wafer. Strained Si technology is based upon the tendency of the Si atoms, when deposited on the Si—Ge buffer layer, to align with the greater lattice constant (spacing) of the Si and Ge atoms therein (relative to pure Si). As a consequence of the Si atoms being deposited on the Si—Ge substrate comprised of atoms which are spaced further apart than in pure Si, they “stretch” to align with the underlying lattice of Si and Ge atoms, thereby “stretching” or tensilely straining the deposited Si layer. Electrons and holes in such strained Si layers have greater mobility than in conventional, relaxed Si layers with smaller inter-atom spacings, i.e., there is less resistance to electron and/or hole flow. For example, electron flow in strained Si may be up to about 70% faster compared to electron flow in conventional Si. Transistors and IC devices formed with such strained Si layers can exhibit operating speeds up to about 35% faster than those of equivalent devices formed with conventional Si, without necessity for reduction in transistor size.
Another tactic for improving the performance of semiconductor devices, e.g., MOS devices such as PMOS and NMOS transistors and CMOS devices, involves increasing the capacitance between the gate electrode and the underlying channel region within the semiconductor substrate. Typically, the capacitance is increased by decreasing the thickness of the gate dielectric layer, typically an oxide layer such as a silicon oxide, to below about 100 Å. Currently, silicon oxide, e.g., SiO
2
, gate dielectric layer thicknesses are approaching about 40 Å or less. However, the utility of silicon oxide as a gate dielectric is severely limited at such reduced thicknesses, e.g., due to direct tunneling through the gate dielectric layer to the underlying channel region, thereby increasing the gate-to-channel leakage current and an increase in power consumption.
Inasmuch as further reduction in the silicon oxide gate dielectric thickness is impractical in view of the above-mentioned increase in gate-to-channel leakage current, various approaches have been investigated for reducing the gate-to-channel leakage current while maintaining a thin SiO
2
“equivalent thickness”, i.e., the thickness of a non-SiO
2
dielectric layer determined by multiplying a given SiO
2
thickness by the ratio of the dielectric constant of the non-SiO
2
dielectric to that of SiO
2
, i.e., k
non-SiO2
/k
SiO2
. Thus, one approach which has been investigated is the use of materials with dielectric constants higher than that of silicon oxide materials as gate dielectric materials, whereby the “high-k” dielectric materials, i.e., materials with dielectric constants of about 5 or above, replace the conventional silicon oxide-based “low-k” dielectric materials with dielectric constants of about 4 or below. The increased capacitance k (or permittivity ∈) of the gate dielectric material advantageously results in an increase in the gate-to-channel capacitance, which in turn results in improved device performance. Since the capacitance C is proportional to the permittivity ∈ of the gate dielectric material divided by the thickness t of the gate dielectric layer, it is evident that the use of a high-k (or high-∈) material permits use of thicker gate dielectric layers, i.e., >40 Å, whereby both greater capacitance and device speed are obtained with less gate-to-channel leakage current.
Typically, high-k dielectric materials, i.e., with k≧5, suitable for use as gate dielectric layers in the manufacture of semiconductor devices, are formed with a physical thickness from about 40 to about 500 Å, typically 40-100 Å (or a SiO
2
equivalent thickness less than about 40 Å), and comprise metal and oxygen-containing material including at least one dielectric material selected from the group consisting of metal oxides, metal silicates, metal aluminates, metal titanates, metal zirconates, ferroelectric materials, binary metal oxides, and ternary metal oxides. Suitable metal oxides include aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, titanium oxide, tantalum oxide, tungsten oxide, cerium oxide, and yttrium oxide; suitable metal silicates include zirconium silicate, and hafnium silicate; suitable metal aluminates include hafnium aluminate and lanthanum aluminate; suitable metal titanates include lead titanate, barium titanate, strontium titanate, and barium strontium titanate; suitable metal zirconates include lead zirconate; and suitable ferroelectric and/or ternary metal oxides include PST (PbSc
x
Ta
1−x
O
3
), PZN (PbZn
x
Nb
1−x
O
3
), PZT (PbZr
x
Ti
1−x
O
3
), and PMN (PbMg
x
Nb
1−x
O
3
). Deposition of the high-k metal oxide layers and/or post-deposition treatment of the high-k metal oxide layers typically involves processing at elevated temperatures, e.g., at about 500-900° C. in the case of aluminum oxide (Al
2
O
3
) deposition from an AlCl
3
/O
2
ambient.
However, an important concern in the manufacture of practical semiconductor devices utilizing strained semiconductor layers, e.g., strained Si layers, is the requirement for maintaining the tensilely strained condition of the strained semiconductor layer throughout device processing, without incurring significant strain relaxation disadvantageously leading to reduction in electron/hole mobility resulting in degradation in device performance characteristics. For example, many device fabrication steps, including for example, the above-described high-k dielectric deposition and post-treatment, frequently involve high temperature processing at temperatures on the order of about 900-1,100° C. for intervals sufficient to result in significant relaxation of the tensile strain of the Si layer, which in turn, results in a lowering of the electron and hole mobilities therein to values comparable to those of conventional Si layers, whereby the potential advantages attributable to enhanced electron/hole mobility in the strained Si layer are partially or wholly lost.
Accordingly, there exists a need for improved methodology for fabrication of semiconductor devices with strained semiconductor layers, notably strained Si layers, which substantially eliminates, or at least minimizes, deleterious stress relaxation during device processing at elevated temperatures, e.g., as in the formation of high-k dielectric gate insulator layers as part of a process sequence for the manufacture of MOS-type transistors and CMOS devices.
The present invention, wherein processing for deposition of high-k dielectric ga

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