Formation of finely controlled shallow trench isolation for...

Details Formation of finely controlled shallow trench isolation for... Formation of finely controlled shallow trench isolation for...

1999-04-12

2001-01-30

Bowers, Charles (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S296000, C438S427000

Reexamination Certificate

active

06180489

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming planarized shallow trench isolation in the fabrication of integrated circuits.
(2) Description of the Prior Art
Shallow trench isolation (STI) is widely used to provide isolation between active areas, especially in ultra large scale integrated (ULSI) circuit devices. To achieve good planarity after STI, chemical mechanical polishing (CMP) is often used. However, due to pad deformation, the trench open area is susceptible to dishing which causes oxide thinning in the wide trench.
FIG. 1
illustrates a partially completed integrated circuit device of the prior art. A silicon nitride layer
14
has been deposited over the surface of a semiconductor substrate
10
. Trenches in the substrate have been filled with an oxide
17
. Referring to
FIG. 2
, the oxide
17
is polished using CMP. Oxide dishing and the resulting lack of oxide uniformity can both be seen in area
19
.
A number of workers in the art have sought to avoid these problems. U.S. Pat. No. 4,962,064 to Haskell et al teaches the use of a polysilicon layer over the oxide trench fill material. The oxide material is then planarized with a series of alternating CMP and dry or wet etches including at least two of each. U.S. Pat. No. 5,494,857 to Cooperman et al teaches CMP of shallow trenches using a reverse-tone mask to form oxide blocks in the wide trenches and a silicon nitride polish stop layer. U.S. Pat. No. 5,641,704 to Paoli et al discloses filling trenches with a first conformal oxide, a planarizing oxide, and then a second conformal oxide. The fill material is planarized by chemical etching the active areas through a mask, then CMP, followed by chemical etching with an etch stop at the silicon nitride layer. U.S. Pat. No. 5,492,858 to Bose et al shows a silicon nitride liner deposited in the trench before the oxide filler. The oxide is then steam annealed, followed by a resist etchback step and CMP. U.S. Pat. No. 5,663,107 to Peschke et al uses a doped glass as a fill material with silicon nitride thereover. Planarization includes CMP, isotropic etch back, dry etching to remove the nitride, and a second CMP step.
SUMMARY OF THE INVENTION
Accordingly, the primary object of the invention is to provide a process for forming planarized shallow trench isolation in the fabrication of integrated circuits.
A further object of the invention is to provide a process for forming planarized shallow trench isolation in which oxide dishing is eliminated.
Still another object is to provide a process for forming planarized shallow trench isolation in which remaining oxide thickness is easily controlled.
Yet another object of the invention is to provide a process for forming planarized shallow trench isolation comprising chemical mechanical polishing followed by dry etching.
In accordance with the objects of the invention, a method for forming planarized shallow trench isolation is achieved. A nitride layer is deposited over the surface of a semiconductor substrate. A plurality of isolation trenches are etched through the nitride layer into the semiconductor substrate wherein there are at least one wide trench and at least one narrow trench. A first oxide layer is deposited over the first nitride layer and within the isolation trenches wherein the first oxide layer fills the isolation trenches. A capping nitride layer is deposited overlying the first oxide layer. A second oxide layer is deposited overlying the capping nitride layer. The second oxide layer is polished away wherein the second oxide layer and the capping nitride layer are left only within the wide trench. The first and second oxide layers are dry etched away with an etch stop on the capping nitride layer within the wide trench and the first nitride layer wherein the second oxide layer is completely removed. Thereafter, the first oxide layer is overetched to leave the top surface of the first oxide layer just above the bottom surface of the first nitride layer and the capping nitride layer within the wide trench. The capping nitride layer and the first nitride layer are removed completing the formation of shallow trench isolation regions in the fabrication of an integrated circuit device.


REFERENCES:
patent: 4962064 (1990-10-01), Haskell et al.
patent: 5492858 (1996-02-01), Bose et al.
patent: 5494857 (1996-02-01), Cooperman et al.
patent: 5641704 (1997-06-01), Paoli et al.
patent: 5663107 (1997-09-01), Peschke et al.
patent: 5719085 (1998-02-01), Moon et al.
patent: 5728621 (1998-03-01), Zheng et al.
patent: 5780346 (1998-07-01), Arghavani et al.
patent: 5817567 (1998-10-01), Jang et al.
patent: 5872043 (1999-02-01), Chen
patent: 5923993 (1999-07-01), Sahota
patent: 6033970 (2000-03-01), Park
patent: 6048771 (2000-04-01), Lin et al.
patent: 6048775 (2000-04-01), Yao et al.
patent: 6057210 (2000-05-01), Yang et al.
patent: 6071792 (2000-06-01), Kim et al.

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