Formation of electrical interconnect lines by selective...

Details Formation of electrical interconnect lines by selective... Formation of electrical interconnect lines by selective...

2000-06-07

2001-07-10

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S629000, C438S631000, C438S669000, C438S672000

Reexamination Certificate

active

06258709

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a metallization method in the manufacture of semiconductor devices, and more particularly to the formation of electrical interconnect lines by a selective metal etch to form electrical interconnections between different layers in a semiconductor device.
Integrated circuits are manufactured by an elaborate process in which a variety of different electronic devices are integrally formed on a small silicon wafer. Conventional electronic devices include capacitors, resistors, transistors, diodes, and the like. In advanced manufacturing of integrated circuits, hundreds of thousands of electronic devices are formed on a single wafer.
One of the steps in the manufacture of integrated circuits is to form metal interconnect lines between the discrete electronic devices on the integrated circuit. The metal interconnect lines allow for an electrical current to be delivered to and from the electronic devices so that the integrated circuit can perform its intended function.
The metal interconnect lines generally comprise narrow bands of aluminum, copper, or other conductive metal. Aluminum has typically been used because it has a relatively low resistivity, good current-carrying density, superior adhesion to silicon dioxide, and is available in high purity. Each of these properties is desirable in interconnect lines as they result in a faster and more efficient electronic circuit.
The computer industry is constantly under market demand to increase the speed at which integrated circuits operate and to decrease the size of integrated circuits. To accomplish this task, the electronic devices on a silicon wafer are continually being increased in number and decreased in dimension. In turn, the dimension of the metal interconnect lines must also be decreased. This process is known as miniaturization.
Metal interconnect lines are now believed to be one of the limiting factors in the miniaturization of integrated circuits. It has been found, however, that by using more than one level in the interconnect, the average interconnect link is reduced and with it the space required on the integrated circuit. Thus, integrated circuits can further be reduced in size. These multi-level metals are referred to as metal interconnect stacks, named for the multiple layers of different metals which are stacked on top of each other. The interconnection features are sometimes referred to as vias or contacts. Reliable formation of these interconnect features is very important to the successful production of semiconductor devices and to the continued effort to increase circuit density.
One known procedure for the fabrication of semiconductor devices is illustrated in
FIGS. 1
a
-
1
d
which, in cross-sectional schematic diagrams, illustrate a stacked-layer semiconductor structure
10
which includes a dielectric layer
12
formed over an underlying layer
14
which contains electrically conductive features
16
. Alternatively, the entire underlying layer
14
may be electrically conductive and may comprise a metal or doped silicon layer. Dielectric layer
12
typically comprises an oxide such as silicon oxide and is formed in a manner which is conventional in the art. Typically, dielectric layer
12
is termed an interlayer dielectric (ILD) as its purpose is to isolate metal features in different layers in the stack. Generally, a metal or electrically conductive feature in the layer of the semiconductor structure immediately beneath the dielectric layer may be termed metal layer
1
or M1, and any metal or electrically conductive feature immediately above dielectric layer
12
may be termed metal layer
2
or M2.
As shown in
FIG. 1
b
, once dielectric layer
12
has been deposited, it is etched using conventional photolithography masking and etching techniques to form vias or openings
18
which expose the surface of electrically conductive features
16
. Referring now to
FIG. 1
c
, via
18
is then filled with a conductive material such as a metal
20
to provide electrical contact with electrical feature
16
. Metal
20
may be deposited by any conventional process. Typically, the upper surface of structure
10
is then planarized. Finally, as shown in
FIG. 1
d
, one or more metal layers or other electrically conductive features
22
are provided, typically by photolithography masking and deposition techniques. For example, features
22
may be provided by patterning a photo mask and removing the patterned areas, followed by depositing the metal into the open areas in the pattern. Once the metal is deposited, the remainder of the photo mask material is removed.
However, this prior art technique suffers from a number of problems. One significant problem is that the etching process to remove portions of the dielectric layer
12
leaves behind polymeric debris and other contaminants in vias
18
. Such materials are difficult to clean out completely and interfere with the subsequent metal deposition step and prevent making good electrical contacts between the M1 and M2 layers. Further, as the widths of vias
18
are quite small, the positioning of the patterning photo masks must be precise, as any misalignment may result in a missed connection or only partial alignment of the M1 and M2 features. To address this alignment problem, in some instances the metal features on the M1 level have had to be patterned to increase their apparent surface area by adding what are termed “surrounds.” However, this adds additional processing steps and further complicates the fabrication of the devices and makes miniaturization more difficult.
Another known procedure for forming the electrical interconnect lines between layers is known as the “dual damascene” process, of which there are numerous variations. Generally, the dual damascene process uses two sequential photoresist and etch steps to form a first opening or via through an oxide layer to an underlying metal line. A second in-line opening is made to form a conductive line above the via. Thus, two photoresist and etch steps are used to form a combined via and line in the oxide layer. Any remaining materials, including contaminants and other debris resulting from the etch process, must be cleaned out of the resulting via. Both openings are then filled with a conductive metal such as aluminum or copper, typically using sputter deposition or CVD processes. In most instances, there is a need for the formation of seed layers or barrier layers for the conductive metal. After the conductive metal has been deposited, excess metal is removed by mechanical or chemical mechanical polishing of the surface to produce a planarized surface. However, such polishing steps also tend to remove some of the oxide layer as well.
Current methods used in this art, including the dual damascene method and its variations, have drawbacks in the formation of electrical interconnect lines including the need to etch through an oxide layer to form the vias (resulting in the need for contaminant removal and cleaning), misalignment of vias, and increasingly high aspect fill ratios for the electrical contact material as the size of interconnect lines continues to shrink. Accordingly, a need still exists in this art for a process for forming electrical interconnect lines which does not have the drawbacks of prior processes.
SUMMARY OF THE INVENTION
The present invention meets that need by providing a process for the formation of electrical interconnect lines by a selective metal etch to form electrical interconnections between different layers in a semiconductor device. The process of the present invention has several advantages including the elimination of the need to form a via by etching through an oxide layer, resulting in a construction which provides superior electrical contacts between electrically conductive features on different layers of the semiconductor device. Additionally, the process of the present invention produces self-aligned vias, thereby eliminating misalignment problems and the need to pattern surrounds onto the M1 layer or any other low

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