Formation of dual polarity source/drain extensions in lateral co

Details Formation of dual polarity source/drain extensions in lateral co Formation of dual polarity source/drain extensions in lateral co

1992-08-05

1994-08-16

Wojciechowicz, Edward

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257327, 257338, 257369, 257408, 257409, 437 41, 437 56, 437 58, 437150, 437152, 437913, H01L 2968, H01L 21265

Patent

active

053389603

ABSTRACT:
Dual polarity source/drain extensions are formed simultaneously in both PMOS and NMOS devices of a CMOS architecture using a common set of implants, so to be contiguous with one or both of source and drain regions of both the PMOS and the NMOS structures. The complementary conductivity lateral extension region configuration may be either an N over P or a P over N structure. The dual implant methodology can be carried out with no explicit masking steps, yielding MOS device which have source/drain extension regions that are self aligned to the gate and have minimal overlap capacitance.

REFERENCES:
patent: 5170232 (1992-12-01), Narita

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