Formation of dielectric regions of different thicknesses at...

Details Formation of dielectric regions of different thicknesses at... Formation of dielectric regions of different thicknesses at...

2000-12-11

2002-07-23

Everhart, Caridad (Department: 2825)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

C438S765000, C438S795000, C438S770000

Reexamination Certificate

active

06423647

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to fabrication of integrated circuits, and more particularly, to fabrication of dielectric regions of different thicknesses by controlling the laser power used for forming a respective dielectric at each of selective location areas defined by a respective opening through a respective layer of metal during laser thermal processes.
BACKGROUND OF THE INVENTION
The present invention is described for fabricating dielectric regions of different thicknesses for gate dielectrics of field effect transistors having different threshold voltages. However, the present invention may be advantageously used for fabricating dielectric regions of different thicknesses for other integrated circuit applications, as would be apparent to one of ordinary skill in the art of integrated circuit fabrication from the description herein.
Referring to
FIG. 1
, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
which is fabricated within a semiconductor substrate
102
. The MOSFET
100
includes a drain extension junction
104
and a source extension junction
106
formed within an active device area
126
of the semiconductor substrate
102
. The drain extension junction
104
and the source extension junction
106
are relatively shallow junctions to minimize short-channel effects in the MOSFET
100
having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET
100
further includes a drain contact junction
108
with a drain silicide
110
for providing contact to the drain of the MOSFET
100
and includes a source contact junction
112
with a source silicide
114
for providing contact to the source of the MOSFET
100
. The drain contact junction
108
and the source contact junction
112
are fabricated as deeper junctions such that a relatively large size of the drain silicide
110
and the source silicide
114
respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET
100
.
The MOSFET
100
further includes a gate dielectric
116
and a gate structure
118
which may be comprised of polysilicon. A gate silicide
120
is formed on the polysilicon gate structure
118
for providing contact to the gate of the MOSFET
100
. The MOSFET
100
is electrically isolated from other integrated circuit devices within the semiconductor substrate
102
by shallow trench isolation structures
121
. The shallow trench isolation structures
121
define the active device area
126
, within the semiconductor substrate
102
, where a MOSFET is fabricated therein.
The MOSFET
100
also includes a spacer
122
disposed on the sidewalls of the gate structure
118
and the gate dielectric
116
. When the spacer
122
is comprised of silicon nitride (Si
3
N
4
), then a spacer liner oxide
124
is deposited as a buffer layer between the spacer
122
and the sidewalls of the gate structure
118
and the gate dielectric
116
.
MOSFETs with different threshold voltages in an integrated circuit may be desired. For example, a MOSFET operating with lower bias voltages for low power applications is desired to have a low threshold voltage to ensure that the MOSFET turns on with such lower bias voltages. On the other hand, a MOSFET operating with higher bias voltages for enhanced speed performance is desired to have a higher threshold voltage to ensure that the gate dielectric
116
does not break down with such higher bias voltages. The thickness of the gate dielectric
116
determines the threshold voltage of the MOSFET
100
with a thinner gate dielectric
116
resulting in a lower threshold voltage, as known to one of ordinary skill in the art of integrated circuit fabrication.
Because MOSFETs with different threshold voltages may be desired for an integrated circuit fabricated on a semiconductor substrate, a mechanism is desired for fabricating gate dielectrics of different thicknesses on the semiconductor substrate.
SUMMARY OF THE INVENTION
Accordingly, in a general aspect of the present invention, dielectric regions of different thicknesses are fabricated by controlling the laser power used for forming a respective dielectric at each of selective location areas defined by a respective opening through a respective layer of metal during laser thermal processes.
In one embodiment of the present invention, in a method for fabricating regions of dielectric material on a semiconductor substrate, a first layer of metal is deposited on the semiconductor substrate, and a first opening is etched through the first layer of metal at a first location area on the semiconductor substrate. First laser beams having a first laser power are directed toward the semiconductor substrate to form a first region of dielectric material having a first thickness at the first location area on the semiconductor substrate. The first layer of metal reflects the first laser beams away from the semiconductor substrate except at the first location area, and the first thickness of the first region of dielectric material is determined by the first laser power of the first laser beams. The first layer of metal is removed from the semiconductor substrate.
A second layer of metal is then deposited on the semiconductor substrate, and a second opening is etched through the second layer of metal at a second location area on the semiconductor substrate. Second laser beams having a second laser power are directed toward the semiconductor substrate to form a second region of dielectric material having a second thickness at the second location area on the semiconductor substrate. The second layer of metal reflects the second laser beams away from the semiconductor substrate except at the second location area, and the second thickness of the second region of dielectric material is determined by the second laser power of the second laser beams. The second layer of metal is then removed from the semiconductor substrate.
The present invention may be used to particular advantage when the semiconductor substrate is comprised of silicon, when the first region of dielectric material and the second region of dielectric material are comprised of silicon dioxide (SiO
2
), when the layer of metal is comprised of aluminum, and when the first laser beams and the second laser beams have a wavelength of about 308 nm (nanometers).
In addition, in one embodiment of the present invention, the first laser power of the first laser beams is less than the second laser power of the second laser beams such that the first thickness of the first region of dielectric material is less than the second thickness of the second region of dielectric material. In that case, the present invention may be used to particular advantage when the first region of dielectric material forms a gate dielectric of a first field effect transistor having a first threshold voltage, and when the second region of the dielectric material forms a gate dielectric of a second field effect transistor having a second threshold voltage, such that the first threshold voltage of the first field effect transistor is lower than the second threshold voltage of the second field effect transistor.
In this manner, by oxidizing the semiconductor substrate at selective location areas defined by a respective opening through a respective layer of metal in a laser thermal process with variation of the laser power, multiple location areas of gate dielectrics of different thicknesses may be formed for field effect transistors with different threshold voltages of an integrated circuit.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.


REFERENCES:
patent: 5718991 (1998-02-01), Lin et al.
patent: 5904575 (1999-05-01), Ishida et al.
patent: 6319759 (2001-11-01), Furukawa et al.

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