Formation of deep via airgaps for three dimensional wafer to...

Details Formation of deep via airgaps for three dimensional wafer to... Formation of deep via airgaps for three dimensional wafer to...

2005-12-16

2008-03-04

Ghyka, Alexander (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S456000, C438S459000

Reexamination Certificate

active

07338896

ABSTRACT:
A method for forming deep via airgaps in a semiconductor substrate is disclosed comprising the steps of patterning a hole in the substrate, partly fill said hole with a sacrificial material (e.g. poly-Si), forming spacers on the sidewalls of the unfilled part of the hole (e.g. TEOS) to narrow the opening, removing through said narrowed opening the remaining part of the sacrificial material (e.g. by isotropic etching) and finally sealing the opening of the airgap by depositing a conformal layer (TEOS) above the spacers. The method of forming a deep via airgap is used to create wafer to wafer vertical stacking. After completion of conventional FEOL and BEOL processing the backside of the wafer will be thinned such that the deep via airgap is opened and conductive material can be deposited within said (airgap) via opening and a through wafer or deep via filled with conductive material is created.

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