Formation of composite monosilicon/polysilicon layer using reduc

Details Formation of composite monosilicon/polysilicon layer using reduc Formation of composite monosilicon/polysilicon layer using reduc

1990-12-19

1992-05-05

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 99, 437108, 437233, 148DIG25, 148DIG27, H01L 2120

Patent

active

051107570

ABSTRACT:
A reduced-temperature two-step silicon deposition performed at different silicon sources is used in forming a composite monosilicon/polysilicon layer (20/24/26) on a body that contains a monosilicon region (10) and an adjoining dielectric regin (12). The first step entails selectively depositing silicon, preferably using dichlorosilane as a CVD silicon source, to grow a first monosilicon layer (20) on exposed monosilicon at an average body temperature less than or equal to 950.degree. C. Substantially no silicon accumulates on exposed dielectric material during the first step. The second step entails non-selectively depositing silicon, preferably using silane as a CVD silicon source, at an average body temperature less than or equal to 950.degree. C. to grow a second monosilicon layer (24) on the first monosilicon layer and to simultaneously grow a polysilicon layer (26) on the exposed dielectric material.

REFERENCES:
patent: 3600651 (1971-08-01), Duncan
patent: 4270960 (1981-06-01), Bollen et al.
patent: 4497683 (1985-02-01), Celler et al.
patent: 4637127 (1987-01-01), Kurogi et al.
patent: 4698316 (1987-10-01), Corboy, Jr. et al.
patent: 4728389 (1988-03-01), Logar
patent: 4855258 (1989-08-01), Allman et al.
patent: 4882294 (1989-11-01), Christenson
patent: 4966861 (1990-10-01), Mieno et al.
patent: 4986787 (1991-01-01), Olivier et al.
Diguichi et al., "Advanced Bipolar Process Using Selective Poly-and Epitaxial-Si (SPEG) Technique", Tech. Dig., 1987, Int'l Elec. Devs, 1987, 835-37.
Mieno et al., "Low Temperature Epitaxy Using Si.sub.2 H.sub.6 ", Extended Abs, Electrochem. Soc., vol. 87-1, Abst. 258, 1987, pp. 374-375.
Yamataki et al., "Epitaxially Grown Base Transistor for High-Speed Operation", IEEE Elec. Dev. Lett., Nov. 1987, pp. 528-530.
Nakazato et al., "A 3 GHz Lateral PNP Transistor", Tech. Dig., Int'3 l Elec. Devs. Mtg., 1986, pp. 416-419.
Borland et al., "Advanced Dielectric Isolation Through Selective Epitaxial Growth Techniques", Solid State Tech., Aug. 1985, pp. 141-148.
"Smooth Polysilicon Films Using Dichlorosilane", IBM Tech. Discl. Bull., Sep. 1986, pp. 1689-1691.
Claassen et al., "The Nucleation of CVD Silicon on SiO.sub.2 and Si.sub.3 N.sub.4 Substrates, I. The SiH.sub.4 -Hcl-H.sub.2 System at High Temperatures", J. Electrochem. Soc., Solid-State Sci. and Tech., Jan. 1980, pp. 194-202.
Wolf et al., Silicon Processing for the VLSI Era (Lattice Press, 1986), vol. 1, pp. 133-136 and 155-156.
Mieno et al., "Novel Selective Poly and . . . ", Tech. Dig., 1987, Int'l Elec Devs. Mtg., 1987, pp. 16-19.

Affiliated with

Also associated with

Rating

Formation of composite monosilicon/polysilicon layer using reduc does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Formation of composite monosilicon/polysilicon layer using reduc, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Formation of composite monosilicon/polysilicon layer using reduc will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1412183