Formation of an integrated circuit structure with reduced...

Details Formation of an integrated circuit structure with reduced... Formation of an integrated circuit structure with reduced...

2007-01-03

2010-06-01

Nguyen, Ha Tran T (Department: 2829)

Semiconductor device manufacturing: process

Chemical etching

Combined with coating step

C438S631000, C438S637000, C438S691000, C438S692000

Reexamination Certificate

active

07727894

ABSTRACT:
An integrated circuit structure includes a metallization level having a dual damascene trench structure formed in a layer of dielectric material. The dielectric material has an upper surface with a first degree of planarity. The metallization level includes a conductive layer formed in the trench structure with an upper surface characterized by the same level of planarity as the dielectric material upper surface. In certain embodiments, the upper surface of the conductive layer is substantially coplanar with the dielectric material upper surface.

REFERENCES:
patent: 6653224 (2003-11-01), Gotkis et al.
patent: 2002/0048934 (2002-04-01), Shieh et al.
patent: 2006/0249482 (2006-11-01), Wrschka et al.

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