Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of...
Reexamination Certificate
1999-07-26
2001-06-26
Picardat, Kevin M. (Department: 2823)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
C438S400000, C438S421000, C438S619000
Reexamination Certificate
active
06251798
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of Integrated Circuit devices, and more specifically to Plasma Enhanced Chemical Vapor Deposition (PECVD) Plasma Polymerized Methylsilane (PPMS) processing and the formation of air gaps as a low dielectric constant material between conductor lines.
(2) Description of the Prior Art
The formation of air gaps between conducting lines of high speed Integrated Circuits (IC's) is typically a combination of the deposition of a metal layer, selective etching of the metal layer to form the desired line patterns, the deposition of a porous dielectric layer or a disposable liquid layer which is then selectively removed to form the desired air-gaps.
The continuing effort to reduce the size of individual transistors and other devices commonly integrated on a semiconductor chip and to increase the density of Integrated Circuits results in a continuing reduction of the separation between conducting layers of materials. This reduction results in an increase of capacitive crosstalk between adjacent conductor lines of a semiconductor circuit, that is the voltage on the first conductor line alters or affects the voltage on the second conductor line. This alteration in voltage can cause erroneous voltage levels in the Integrated Circuit making the IC increasingly prone to faulty operation. It becomes therefore imperative to reduce the resistive capacitance (RC) time constant and the crosstalk between adjacent conducting lines.
The capacitance between adjacent conducting lines is highly dependent on the insulator or dielectric used to separate the conducting lines. Conventional semiconductor fabrication typically uses silicon dioxide as a dielectric; this has a dielectric constant of about 3.9.
The use of many of the low dielectric constant materials is not feasible due to the fact that equipment is not available to properly process the new dielectric material in various integrated circuits. Also, the chemical or physical properties of many low dielectric constant materials are usually difficult to make compatible with or integrate into conventional integrated circuit processing.
The lowest possible and therefore the ideal dielectric constant is 1.0, this is the dielectric constant of a vacuum whereas air has a dielectric constant of less that 1.001.
To reduce said capacitive coupling and reduce the capacitive crosstalk, a major objective in the design of IC's is to reduce the Dielectric Constant (k) of the insulating layer between adjacent conductor lines of semiconductor circuits. The present invention makes a significant contribution within the scope of this effort.
U.S. Pat. No. 5,461,003 (Haveman et al.) shows a method of forming air gaps between metal lines by: 1) forming a photoresist layer (disposable layer)
18
(see table 1) between and over metal lines; 2) forming a low-k dielectric (PPMA) (
20
see table 1) (but not by having openings thereover); 3) removing the PPMA
18
and thereby forming air gaps and 4) by forming a capping oxide layer to close up the air gaps. However, this patent differs from the present invention.
U.S. Pat. No. 5,510,293 (Numate) and U.S. Pat. No. 5,372,969 (Moslehi) show air gap processes.
U.S. Pat. No. 5,468,685 (Orisaka et al.) shows a porous dielectric layer.
SUMMARY OF THE INVENTION
The principal object of the present invention is to provide an effective and manufacturable method of forming air gaps between conductive layers of material.
Another objective of the present invention is a method of reducing the dielectric constant k between conductive layers of material.
Another objective of the present invention is a method of reducing capacitive coupling between conducting layers of material.
Another objective of the present invention is a method of reducing capacitive crosstalk between conductive layers of material.
Another objective of the present invention is to reduce the potential for false or incorrect logic levels of the circuits in the IC's.
Another objective of the present invention is a method of reducing Resistive Capacitive delays of the circuits in the IC's.
Another objective of the present invention is to increase Switching Speed of the circuits in the IC's.
In accordance with the objects of the present invention a new method of forming air gaps between adjacent conducting lines of a semiconductor circuit is achieved.
A metal pattern of metal lines is in the standard manner deposited on a semiconductor substrate. A layer of Plasma Polymerized Methylsilane (PPMS) resist is deposited on top of this pattern using Plasma Enhanced Chemical Vapor Deposition (PECVD). Chemical Mechanical Polarization (CMP) is performed to achieve planarity of the deposited PPMS resist. This step is optional.
A reticle is interposed between a source of radiation and the surface of the created PPMS resist. The surface of the PPMS resist is subjected to deep ultraviolet (UV) exposure (with radiation wavelength of 193 nm., 248 nm., etc.) or by E-beam radiation. The exposure depth is controlled during this exposure. The surface of the PPMS resists is selectively (via the reticle) exposed, the PPMS is bleached or exposed down to slightly below the top of the metal lines, the PPMS is in this manner converted to PPMSO. Columns of unexposed PPMS are created in the areas that are protected or shielded by the reticle. The PPMS is removed by normal polymer remove methods such as oxygen plasma. The process is completed by closing up the openings between the PPMSO columns by oxide CVD across the surface of the structure.
REFERENCES:
patent: 5372969 (1994-12-01), Moslehi
patent: 5461003 (1995-10-01), Havemann et al.
patent: 5468685 (1995-11-01), Orisaka et al.
patent: 5510293 (1996-04-01), Numata
Chan Lap
Ong Kok Keng
Soo Choi Pheng
Tee Kheng Chok
Chartered Semiconductor Manufacturing Company
Collins D. M.
Picardat Kevin M.
Pike Rosemary L.S.
Saile George O.
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