Formation of a vertical junction through process simulation...

Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region

Reexamination Certificate

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Details

C438S228000

Reexamination Certificate

active

06362080

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to semiconductor devices. More specifically, the invention relates to ion implantation used in making semiconductor devices.
BACKGROUND OF THE INVENTION
In the formation of semiconductor devices in integrated circuit chips, an isolation edge region may be formed to separate an N-doped region from a P-doped region.
To facilitate discussion,
FIG. 1
is a schematic view of an isolation junction between an N-doped region
104
, such as an N-well, and a P-doped region
108
, such as a P-well, in a substrate
112
. The N-doped region
104
may be formed by an ion implantation of an N-type dopant. The P-doped region
108
may be formed by an ion implantation of a P-type dopant. A spacer
116
may be used to separate the N-doped region
104
from the P-doped region
108
. Both the N-doped region
104
and the P-doped region
108
extend under the spacer
116
due to lateral straggle of the implanted dopant and due to the lateral diffusion during temperature cycling. Lateral straggle is caused by implantation of the dopant in the substrate. Both lateral implant straggle and lateral diffusion may cause the N-doped region
104
to have a bowed shape
120
that extends under the spacer
116
. In the prior art, lateral straggle may be about 0.7 times the depth of the junction while diffusion will cause dopant to move laterally as much as it does vertically. So for a junction with a 0.5 micron depth, the lateral straggle may be 0.35 microns. Lateral diffusion causes even more lateral travel. Providing space to accommodate the bowed shape
120
of the N-doped region
104
and the lateral
2
d
dopant profile of the P-doped region
108
, caused by both lateral straggle and lateral diffusion, may waste chip real estate.
If the space required by the NP isolation junction could be reduced, the resulting chip size may also be reduced. It is desirable to provide a more compact NP junction to reduce the size of a semiconductor device.
SUMMARY OF THE INVENTION
To achieve the foregoing and other objects and in accordance with the purpose of the present invention, a variety of techniques is provided for forming an isolation junction between a region of a first conductivity type and a region of a second conductivity type in a substrate. Generally, a first series of dopings of a first conductivity type is provided. The first mask is then removed. A second mask is formed over a part of the surface of the substrate, wherein part of the surface covered by the first mask is not covered by the second mask and wherein part of the surface covered by the second mask was not covered by the first mask. A second series of dopings of a second conductivity type is provided, wherein the first series of dopings and the second series of dopings form a substantially vertical junction.
The present invention also provides a variety of techniques for determining a recipe for creating a vertical junction. Generally a first mask is specified. A first series of dopings is also specified. The removal of the first mask is then specified. A second mask is then specified. A second series of dopings of a second conductivity type is then specified. The resulting junction position is then determined. The first series of dopings and second series of dopings are then respecified to reduce a difference between the resulting junction position and a line through the junction.
The present invention also provides a region in a semiconductor substrate. The region has a P-doped region and an N-doped region in the substrate, where the N-doped region is adjacent to the P-doped region. A substantially vertical junction separates the P-doped region from the N-doped region.


REFERENCES:
patent: 4697332 (1987-10-01), Joy et al.
patent: 5753956 (1998-05-01), Honeycutt et al.
patent: 6066523 (2000-05-01), Shim et al.
patent: 6242294 (2001-06-01), Mitani et al.

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