Formation and planarization of silicon-on-insulator structures

Details Formation and planarization of silicon-on-insulator structures Formation and planarization of silicon-on-insulator structures

1985-12-23

1986-08-05

Massie, Jerome

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

29576W, 29580, 156643, 156649, 156653, 156662, 156668, 427 94, 427 95, 427308, 427337, 427399, 4274071, H01L 21308, H01L 21312, H01L 21318

Patent

active

046041621

ABSTRACT:
A process for fabricating silicon-on-insulator structures on semiconductor wafers and planarizing the topology of the patterns formed from the silicon. In the composite, the process provides for the formation of monocrystalline silicon islands electrically isolated by dielectric in substantially coplanar arrangement with surrounding dielectric. According to one practice of the process, substrate silicon islands are initially formed and capped, and thereafter used as masks to direct the anisotropic etch of the silicon substrate to regions between the islands. During the oxidation which follows, the capped and effectively elevated silicon islands are electrically isolated from the substrate by lateral oxidation through the silicon walls exposed during the preceding etch step. The capped regions, however, remain substantially unaffected during the oxidation. With the electrically isolated silicon island in place, a silicon dioxide layer and a planarizing polymer layer are deposited over the wafer. Processing is concluded with a pair of etching operations, the first removing polymer and silicon dioxide at substantially identical rates, and the second removing silicon dioxide and monocrystalline silicon at substantially identical rates.

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