Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-02-01
2004-03-30
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06715135
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a formal verification method for verifying the function of a logic circuit.
2. Description of the Related art
Semiconductor integrated circuits such as a system LSI are advancing in functionality and increasing in logic scale. Accordingly, the logic verification of the semiconductor integrated circuits tends to become increasingly greater both in verification scale and in verification time.
Recently, attention has been given to formal verification as one of the techniques for logic verification. The formal verification is one in which a logic circuit modeled, for example, in RTL expressions is converted into a finite state machine, followed by a mathematical proof that the specifications to be verified are satisfied. The formal verification is superior in exhaustiveness as compared to conventional simulation methods which take account of input patterns alone. Therefore, it is possible to detect errors which are hard to find in simulations.
The formal verification is, however, higher than logic simulations in computational complexity. Therefore, in handling a circuit model having a large number of states, the workstation executing the verification program can sometimes run out of memory capacity and becomes unable to verify. Upon a verification failure due to insufficient memory, the verification program is terminated forcefully. This has presented a problem of the absence of the verification results. That is, there has been a problem that when the verification program is terminated forcefully, it is impossible to confirm how far the verification has been made. In some cases, a formal verification requires an execution time as long as one week or so. Accordingly, forced termination can cause extremely heavy losses in terms of time and cost.
The scale of a circuit model capable of formal verification depends largely on the number of flip-flops contained in the model. Theory holds that the number of states of a circuit model is twice the increment of flip-flops. The memory capacity required for the verification also doubles accordingly. In the meantime, since the formal verification is characterized in the exhaustiveness of input patterns as mentioned above, it is difficult to estimate the memory capacity and the verification time required for the verification accurately. Therefore, simply adding a memory to the workstation will not always promise the proper execution of the formal verification until the end.
As mentioned above, the formal verification is extremely useful for verifying a logic circuit, whereas no consideration has been given to the forced termination owing to insufficient memory which is relatively likely to occur.
SUMMARY OF THE INVENTION
It is an object of the present invention to improve the efficiency of formal verification by keeping obtained verification results, in cases where forced termination of the verification occurs.
According to one of the aspects of the formal verification method in the present invention, a plurality of input signals to be input to a logic circuit as a verification object is ranked depending on the degrees of influence that the input signals have on operation of the logic circuit. Then, verification is performed with the input signals sequentially given free patterns including all possible input patterns in descending order of the degree of influence. That is, the input patterns are sequentially generated according to preset conditions (the degrees of influence). Therefore, even when the formal verification is forcefully terminated halfway due to such reasons as insufficient memory of a verification apparatus, the obtained verification results until the forced termination can be kept based on the degrees of influence mentioned above. As a result, the causes of the forced termination can be easily analyzed with improved verification efficiency. Since verification-completed input patterns and verification-failed input patterns are distinctive, it is possible to estimate the time taken for the completion of the entire verification and the memory capacity of the verification apparatus required for the verification.
According to another aspect of the formal verification method of the present invention, verification is performed first by giving any of the free patterns to each of the input signals. Thereafter, a plurality of combinations of the input signals is individually given the free patterns for verification, sequentially in descending order of the degree of influence that the combinations have. For example, even in the case where the memory capacity of the verification apparatus is unchanged, a larger number of combinations of input patterns can be verified by sequentially giving input patterns in order of complexity. As a result, it is possible to keep more varieties of verification records.
According to another aspect of the formal verification method in the present invention, each of the input signals other than the input signals given the free patterns is given an input pattern of either “logic 0 fixed” or “logic 1 fixed” for verification. That is, input signals having lower degrees of influence on the operation of the logic circuit are preferentially given either “logic 0 fixed” or “logic 1 fixed.” Since the relationship between the preset conditions (the degrees of influence) and the generated input patterns becomes apparent, the causes of forced termination can be easily analyzed with improved verification efficiency.
According to another aspect of the formal verification method in the present invention, when any of the input signals has a fixed input pattern in the verification of the logic circuit, the input pattern is written in regular expressions. This can reduce the number of signals to be ranked, allowing a reduction in verification time. In addition, the input patterns can be generated easily.
REFERENCES:
patent: 684808 (1901-10-01), Flower
patent: 5452239 (1995-09-01), Dai et al.
Patent Abstracts of Japan of JP 09-114880 dated May 2, 1997.
Do Thuan
Fujitsu Limited
Siek Vuthe
Staas & Halsey , LLP
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