Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate
2007-06-12
2007-06-12
Auduong, Gene N. (Department: 2827)
Static information storage and retrieval
Addressing
Multiple port access
C365S230060, C365S189110
Reexamination Certificate
active
10970452
ABSTRACT:
An apparatus, a method, and a computer program product are provided for time reduction in an array read access control consisting of a bitcell and a pulldown device outside of the bitcell. To reduce gate delay, this design implements a pulldown device that controls the bitcell readout. A pulldown signal is generated to activate the pulldown device. Therefore, the pulldown signal can control the pulling down of the bitcell readout without a complete read of the data array inside the bitcell. This design reduces gate delay because the dependency upon the gating logic is overridden and the number of stages is reduced.
REFERENCES:
patent: 5790454 (1998-08-01), Choi
patent: 2002/0196667 (2002-12-01), Ikehashi et al.
patent: 2006/0083074 (2006-04-01), Cottier et al.
Cottier Scott Raymond
Onishi Shohji
Auduong Gene N.
International Business Machines - Corporation
Rifai D'Ann N.
Tkacs Stephen R.
Walder, Jr. Stephen J.
LandOfFree
Forced pulldown of array read bitlines for generating MUX... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Forced pulldown of array read bitlines for generating MUX..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Forced pulldown of array read bitlines for generating MUX... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3864711