Folded memory layers

Details Folded memory layers Folded memory layers

2002-11-29

2004-07-13

Elms, Richard (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S051000, C365S130000, C365S129000

Reexamination Certificate

active

06762950

ABSTRACT:

The present invention concerns a ferroelectric or electret volumetric memory device, wherein a ferroelectric or electret memory material is provided in sandwich between first and second electrode layers respectively comprising first and second parallel stripe-like electrodes forming word lines and bit lines of a matrix-addressable memory array, wherein word lines and bit lines of the array are oriented substantially at right angles to each other, wherein memory cells are defined in volumes of memory material sandwiched between respective crossings word lines and bit lines, and wherein a plurality of memory arrays are provided in at least one stack such that the at least one stack of memory arrays realizes the memory device with a volumetric configuration.
In a wider sense the present invention also concerns data storage and/or processing devices based on ferroelectric thin films.
No prior art of direct relevance regarding braiding/folding as taught in the present invention has been identified. However, a brief general background shall be given to illustrate the present state of the art, put the present invention into context and highlight the objects of the invention:
Memory chips have the advantage over conventional magnetic, optical and other mechanical storage devices of being capable of very fast read and write operations. Furthermore, they are solid state, have reasonably low power consumption and may offer high transfer speeds. The disadvantage is their limited capacity to store information, and a relatively high production cost relative to the storage capacity. Due to scaling problems and limited area, typically restricted to less than 1 cm
2
/chip, this situation is not likely to be much altered in the foreseeable future.
A solid state memory concept which circumvents the limitations described above has been developed based on hybrid silicon/polymer chips. The approach includes stacking thin layers of polymeric memory films on silicon substrates and accessing the passively addressed memory layers via the substrate circuitry. The problem with this solution, however, is that the number of memory layers in the stack typically is limited to 8-16 layers. Increasing this number is technically possible, but generally not practically viable for most mass market applications. Negative factors in this connection include extra overhead and real estate costs for driver circuitry (decoders and sense amplifiers in particular); reduced yield due to increased number of processing steps; problems associated with planarization when the number of memory layers becomes larger then the range mentioned; and a larger number of processing steps increasing the risk that underlying polymer layers are negatively affected, with a reduced functionality as a result.
There is also an unbalance in the hybrid memory concept to the extent that producing the silicon part is complex and requires advanced (albeit standard) fabrication processing, while building the memory stack in itself is a very simple low cost procedure, which potentially could be done outside fabrication facility, with non-lithographic tools. However, when these stacks are built on silicon the factors listed above combine to make this more costly and capacity limiting than desirable, e.g. it does become more cost effective to use two or several chips to achieve the same capacity.
Also, the procedure used to deposit memory films on silicon is in practice limited to simple spin coating. This deposition technique has several advantages, but may also introduce unwanted side effects, like creating a larger than desirable internal stress, problems in controlling the film morphology and uniformity, etc. One procedure used to improve morphology is stretching of films, which cannot be applied in the hybrid case, another is to anneal films under high pressure which is not very applicable either (when spin coating and rigid substrates like silicon is used).
Because of the area restrictions related to a silicon-based device, the only feasible patterning approach is standard photomicrolithography i.e. providing ahigh resolution line pitch. This excludes low cost, non-lithographic patterning tools like inkjet printing and micropatterning.
Another problem related to the hybrid concept is packaging, especially soldering, which requires temperatures much higher than the melting temperature of polymers (more than 60° C. higher). The polymer does not necessarily destruct when exposed to higher temperatures than its melting temperature, but a rework (reanneal) is required to bring back the film properties. More problematic is what happens to the electrode/film interface, which easily is destroyed when the polymer enters the liquid phase. This represents is substantial problem when multilayer stacks are involved.
Film properties are also seriously affected by electrode application, e.g. the top electrode deposition may have negative effects on the bottom electrode interface, e.g. by kicking off undesired ion transport, which may initiate a fatigue process in the polymer films. Morphological chain defects may also be induced.
In regard of the above-mentioned disadvantages, it is thus a first object of the present invention to provide novel architectures for solid state thin-film-based devices whereby the effective area available for data storage and/or processing can be made large through stacking of individual layers in a dense volumetric structure.
It is a second object of the present invention to prescribe how such stacking can be achieved in a practical manner while at the same time providing individual addressability for locations inside the stack through a limited number of electrical connections that are accessible from the outside of the stack.
It is a third object of the present invention to provide stacks containing a multiplicity of matrices, where each matrix contains a large number of thin-film cells that can be individually connected via passive matrix addressing.
It is a fourth object of the present invention to provide individual stacks in the form of modular units suitable for integration into devices with specialized functions and/or into larger units that add the capacities of two or more separate stacked units.
It is a fifth object of the present invention to apply the stacking concept to the manufacturing of data storage and/or processing devices that contain sub-units demanding mutually incompatible process steps.
The above objects as well as further features and advantages are realized with a memory device which according to the invention is characterized in that a stack of memory arrays is formed with two or more ribbon-like structures being folded and/or braided into each other, each ribbon-like structure comprising a flexible substrate of non-conducting material, that first and second electrode layers respectively, provided on each surface of the substrate, such that the electrode layers each comprises the parallel stripe-like electrodes provided extending along the ribbon-like structure and a layer of memory material covers one of the electrode layers thereof and extends uninterrupted between the edges of the ribbon-like structure, that each memory array of the stack is formed by overlapping portions of a pair of adjacent ribbon-like structures folded and/or braided such that they cross in substantially orthogonal relationship, and that the word lines and the memory layer of a memory array in a stack are contained in the first ribbon-like structure of a pair of adjacent structures of this kind and the bit lines contained in the second ribbon-like thereof.
Further features and advantages of the present invention are disclosed by the dependent claims.


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