Folded bitline, ultra-high density dynamic random access memory

Details Folded bitline, ultra-high density dynamic random access memory Folded bitline, ultra-high density dynamic random access memory

1991-08-05

1993-05-25

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Differential sensing

365 51, 365149, G11C 1300, G11C 1140

Patent

active

052146030

ABSTRACT:
A folded bitline DRAM cell is described which includes a trench capacitor and a planar-configured access transistor. The access transistor is stacked over the capacitor and has a first terminal connected thereto. The access transistor includes a planar-oriented gate. A first wordline has a minor surface in contact with the gate and a major surface that is oriented orthogonally to the gate. An insulating pedestal is positioned adjacent the gate and a passing wordline is positioned on the pedestal, the passing wordline having a major surface parallel to the first wordline. In another embodiment, the folded bitline DRAM cell includes a vertically oriented access transistor having one terminal formed on the upper extent of a contact to the trench capacitor, to provide optimum electrical connection thereto.

REFERENCES:
patent: 4688063 (1987-08-01), Lu et al.
patent: 4734384 (1988-03-01), Tsuchiya
patent: 4798794 (1989-01-01), Ogura et al.
patent: 4873205 (1989-10-01), Critchlow et al.
patent: 4873560 (1989-10-01), Sunami et al.
patent: 4916524 (1990-04-01), Teng et al.
patent: 4922313 (1990-05-01), Tsuchiya
Taguchi et al. "Dielectricly Encapsulated Trench Capacitor Cell" IEDM 86, pp. 136-139.

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