Fly-by serial bus arbitration

Details Fly-by serial bus arbitration Fly-by serial bus arbitration

1998-08-28

2002-05-07

Sheikh, Ayaz (Department: 2155)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S100000, C710S107000, C710S120000, C710S240000, C710S260000

Reexamination Certificate

active

06385679

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to data communications and, more particularly, to data communications in a computer bus architecture.
BACKGROUND OF THE INVENTION
The components of a computer system are typically coupled to a common bus for communicating information to one another. Various bus architectures are known in the prior art, and each bus architecture operates according to a communications protocol that defines the manner in which data transfer between components is accomplished.
The Institute of Electrical and Electronic Engineers (IEEE) has promulgated a number of different bus architecture standards, including IEEE standards document P1394, entitled P1394 High Performance Serial Bus, draft 8.0v3 (hereinafter the “P1394 Serial Bus Standard”). A typical serial bus having the P1394 standard architecture is comprised of a multiplicity of nodes that are interconnected via point-to-point links such as cables that each connect a single node of the serial bus to another node of the serial bus. Data packets are propagated throughout the serial bus using a number of point-to-point transactions, wherein a node that receives a packet from another node via a first point-to-point link retransmits the received packet via other point-to-point links. A tree network configuration and associated packet handling protocol insures that each node receives every packet once. The serial bus of the P1394 Serial Bus Standard may be used as an alternate bus for the parallel back plane bus of a computer system, as a low cost peripheral bus, or as a bus bridge between architecturally compatible buses.
The communications protocol of the P1394 Serial Bus Standard specifies two primary types of bus access: asynchronous access and isochronous access. Asynchronous access may be either “fair” or “cycle-master.” Cycle-master access is used by nodes that need the next available opportunity to transfer data. Isochronous access is used by nodes that require guaranteed bandwidth. The transactions for each type of bus access are comprised of at least one “subaction,” wherein a subaction is a complete one-way transfer operation.
FIG. 1A-1C
show different subactions according to the P1394 Serial Bus Standard.
FIG. 1A
shows a subaction for a fair write transaction.
FIG. 1B
shows a fair broadcast transaction.
FIG. 1C
shows a pair of concatenated subactions used for fair read and lock transactions. The subaction
1
a
of
FIG. 1A
includes an arbitration phase
2
, a data transfer phase
3
, and an acknowledge phase
4
. During the arbitration phase
2
, the arbitration protocol determines which of the nodes that have requested fair access to the serial bus will be granted control of the serial bus. The node that is granted control of the serial bus transmits a data packet on the serial bus during the data transfer phase
3
. For some fair subactions, an acknowledge packet is used to signal receipt of the data packet, and the acknowledge phase
4
is provided so that a destination node may transmit such an acknowledge packet. To transmit the acknowledge packet, the destination node seizes control of the bus without arbitrating for control of the bus. An idle period
5
occurs between the data transfer phase
3
and acknowledge phase
4
. Acknowledge packets are not required for fair broadcast transactions. Accordingly,
FIG. 1B
shows asynchronous broadcast subaction lb, which merely includes the arbitration phase
2
and the data transfer phase
3
.
Two subactions are typically required to complete a read or lock transaction; however, separate arbitration phases are not required for a subaction of the transaction. As shown in
FIG. 1C
, two subactions
1
c
and
1
d
are concatenated together such that there is a single arbitration phase followed by a first data transfer phase, a first idle period, a first acknowledge phase, a second data transfer phase, a second idle period, and a second acknowledge phase.
As shown in each of
FIGS. 1A-1C
, a period of idle time called a subaction gap
6
occurs after a subaction or a concatenated pair of subactions. The subaction gaps
6
shown as preceding each of the subactions
1
a,
1
b
and
1
c
are the subaction gap
6
that occur after a previous subaction (not shown). Each subaction gap
6
is a constant amount of time, T
SA
, that, according to the P1394 Serial Bus Standard, a node must remain idle before it is allowed to initiate the beginning of the arbitration phase for the next subaction. The subaction gap time T
SA
is typically set by system software when the serial bus is initialized.
The insertion of a subaction gap
6
between fair subactions is a result of a simple mechanism used by each node of a typical P1394 serial bus to regulate arbitration timing. For asynchronous bus traffic, each node waits for at least a subaction gap after data transfer before requesting control of the bus. This timing is enforced whether the data transferred by a node is a data packet or an acknowledge packet. The duration of subaction gap
6
is selected to insure that an acknowledge packet is allowed to propagate through the serial bus to the source node before the nodes begin arbitrating for control of the bus. The subaction gap time T
SA
is guaranteed to be of adequate duration if it is defined to be greater than a worse case round trip delay time T
RT
of the serial bus to insure that a possible acknowledge packet is allowed to propagate throughout the serial bus before the nodes begin the arbitration phase of the next subaction. The delay time T
RT
includes the round trip propagation delay between the two nodes of the serial bus having the greatest intervening timing delay. The round-trip propagation delay T
RT
between the nodes is measured from the time that the source node completes transmission of the data packet to the time that the source node begins reception of the acknowledge packet.
The subaction gaps described above are an example of protocol delays in the basic 1394 arbitration operation. Other types of protocol delays, or periods of bus idle time, are arbitration reset gap signals which occur at the end of a fairness intervals. In addition to these protocol delays, other delays on a 1394 bus include propagation delays and operational delays. Propagation delays include cable delays (roughly 5 nanoseconds per meter according to the 1394 Serial Bus Standard), and phy retransmission delays (roughly 140 nanoseconds or less per phy).
Operational delays, for example, the time between a data packet and the acknowledge packet, lie in a gray area between protocol and propagation delays. These operational delays generally depend on propagation delays, implementation details, and the particulars of network topology. Their precise duration is of no significance, provided they do not exceed some maximum value.
Of the various forms of delays, phy retransmission and operational delays are the ones open to engineering improvement. It will be appreciated that protocol delays are dependent on the worse case round trip delay on the bus; as phy retransmission delays improve, the protocol delays will automatically improve as well. Therefore, it would be desirable to minimize the arbitration delays in order to improve bandwidth utilization on the bus.
SUMMARY OF THE INVENTION
Arbitration delays on a serial bus are minimized, according to the methods of the present invention, for a variety of scenarios. In a first embodiment, a node transmits multi-speed concatenated packets without having to go through a separate arbitration request/grant cycle. To accommodate this protocol, the transmitting node first sends a data prefix signal for a first packet. The data prefix includes a speed signal for the first packet. The node then transmits the first data packet. Immediately following the first packet, the node transmits a data prefix, including a speed signal, for a second packet. The second packet then is transmitted. This continues for all packets which the node needs to send. The last packet is followed by a data end signal.
In a second embodiment, a no

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