Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-02-15
2001-08-28
Crane, Sara (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S306000
Reexamination Certificate
active
06281542
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the structure of a semiconductor capacitor in a DRAM cell, and particularly relates to a stacked flower capacitor structure with a large capacitance.
BACKGROUND OF THE INVENTION
Dynamic Random Access Memory (DRAM) devices have been applied in integrated circuits for many years. A DRAM cell is in general a semiconductor memory device with one transistor and one capacitor, in which data of 1-bit can be stored by the charge stored therein. Indeed, a memory cell is provided for each bit stored by a DRAM device. Each memory cell typically consists of a storage capacitor and an access transistor. The source of the access transistor is connected to one terminal of the capacitor. The transistor drain electrode and the gate electrode are connected to external connection lines called a bit line and a word line, respectively. The other terminal of the capacitor is connected to a reference voltage. Therefore, the formation of a DRAM memory cell comprises the formation of a transistor, a capacitor and contacts to the external circuits.
As a tendency to the higher density of an integrated semiconductor device, the density of the DRAM cells is caused to be increased, and the area occupied by one memory cell becomes gradually decreased. Due to this trend of semiconductor devices, the sizes of the memory cells have gotten smaller and smaller. Thus, the area available for a single memory cell has become very small. This has caused a reduction in the area occupied by the capacitor, and has resulted in a reduction of the capacitance of a cell. For the very small memory cells, the planar capacitor has become very difficult for use reliably. Specifically, as the size of the capacitor is decreased, the capacitance of the capacitor is also decreased and the amount of the charge capable of being stored by the capacitor is similarly decreased. Therefore, the present invention is devoted to the manufacture of a capacitor with a maximum capacity in a limited area.
The prior art with the approach to overcome these problems has resulted in the development of the various types of capacitors. One of the capacitors has a bathtub-shaped structure. The process is operated with the characteristic that the staked capacitor has more capacitance than that of the planar type capacitor. In order to increase the capacitance of the capacitor, the thickness of the dielectric film of the capacitor is reduced, and the area of the electrodes of the capacitor is increased by overcoming the limitation of the lithography technique. In other words, the area of the electrodes in one memory cell is increased without the problem of step coverage. Please see “Method For Fabricating Stacked Capacitors In A DRAM Cell,” Jin-Suk Choi. et al., U.S. Pat. No. 5,104,281. Yet, the shape of the storage node of the memory cell is like a bathtub, and the height of the electrode is not extended, so that the area of the electrodes is not largely increased.
Further, a capacitor over bit line (COB) cell with a hemispherical grain silicon storage node has been developed (see “Capacitor Over Bit Line Cell With Hemispherical Grain Storage Node For 64 Mb DRAMs”, M. Sakao et al., Microelectronics Research Laboratories, NEC Corporation, IEDM Tech Dig., December 1990, pp655-658). The HSG-silicon is deposited by low pressure chemical vapor deposition method at the transition temperature from amorphous silicon to polycrystalline silicon. This memory cell provides high capacitance by increasing the effective surface area of a simple storage node. The present invention increases the effective area of the electrodes of the capacitor without the usage of the HSG-silicon, thus the process is simplified.
SUMMARY OF THE INVENTION
The foregoing disadvantages of the traditional structure of a capacitor for a DRAM can be overcome by a new structure that is disclosed herein. A structure of a capacitor on a semiconductor wafer includes the following structures: A first electrode, a first dielectric film, and a second electrode.
The first electrode formed on the semiconductor wafer includes a flower structure. The first electrode includes a flower neck portion, a flower bottom portion, and a flower top portion. The flower neck portion is electrically coupled to the semiconductor wafer, and the flower bottom portion is electrically coupled to the flower neck portion. The flower bottom portion includes a first protudent portion, which overlaps the word line and a gate electrode of the transfer transistor of the semiconductor wafer. The flower top portion includes a downward hemispherical portion and a second protrudent portion. The flower top portion is electrically coupled to the flower neck portion, and the flower top portion is electrically coupled to the flower neck portion by the downward hemispherical portion. In the preferred embodiment of the present invention, the flower bottom portion is formed of titanium nitride, and the flower top portion is formed of Ti/TiN or TiW.
The aforementioned first electrode is electrically coupled to the semiconductor wafer. The first dielectric film is formed on the first electrode, and the first dielectric layer is the dielectric layer of the capacitor. The second electrode is formed on the first dielectric film.
REFERENCES:
patent: 5104821 (1992-04-01), Choi et al.
patent: 5357460 (1994-10-01), Yusuki et al.
patent: 5583359 (1996-12-01), Ng et al.
patent: 5952687 (1999-09-01), Kawakubo et al.
patent: 5973350 (1999-10-01), Wu
patent: 6033919 (2000-03-01), Gnade et al.
patent: 6150690 (2000-11-01), Ishibashi et al.
M. Sakao et al., A Capacitor-Over-Bit-Line (COB) Cell With a Hemispherical-Grain Storage Node for 64Mb DRAMs, 1990 IEEE, pp. 655-658.
Crane Sara
TSMC-Acer Semiconductor Manufacturing Corp.
LandOfFree
Flower-like capacitor structure for a memory cell does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Flower-like capacitor structure for a memory cell, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flower-like capacitor structure for a memory cell will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2501670