Flow for vector capture

Details Flow for vector capture Flow for vector capture

2005-12-27

2005-12-27

Homere, Jean R. (Department: 2128)

Data processing: structural design, modeling, simulation, and em

Simulating electronic device or electrical system

Circuit simulation

C703S013000, C703S017000, C714S724000, C714S738000, C714S741000, C714S744000, C714S745000

Reexamination Certificate

active

06980943

ABSTRACT:
A method and system for generating a synchronous sequence of vectors from information originating within an asynchronous environment is disclosed. A simulated asynchronous sequence is synchronized by extracting a state at each clock period to generate a simulation synchronous sequence. This sequence is manipulated first to include short delays for generating an asynchronous short-delay sequence and second to include long delays for generating an asynchronous long-delay sequence. An overlay is separately performed among the clock periods of the asynchronous short-delay sequence and the asynchronous long-delay sequence to respectively identify a first interval and a second interval. The first interval and the second interval are independently duplicated in successive clock periods to respectively generate a synchronous short-delay sequence and a synchronous long-delay sequence. An overlay is performed on the two sequences to enable generation of the synchronous sequence of vectors for verifying operations of an IC design by a tester.

REFERENCES:
patent: 5448571 (1995-09-01), Hong et al.
patent: 5938785 (1999-08-01), Dargelas
patent: 6101622 (2000-08-01), Lesmeister
patent: 6233707 (2001-05-01), Potter et al.

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