Floorplanning apparatus and computer readable recording...

Details Floorplanning apparatus and computer readable recording... Floorplanning apparatus and computer readable recording...

2011-06-14

2011-06-14

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Integrated circuit design processing

Optimization

C716S132000, C716S118000, C716S119000

Reexamination Certificate

active

07962884

ABSTRACT:
The present invention is aimed to efficiently realize a reduction in size of and dead space in a semiconductor integrated circuit while securing freedom of placement and wiring of internal components of placement objects and suppressing an increase of constraints of CAD system. A floorplanning apparatus has a temporary placement section temporarily arranging a plurality of placement object blocks onto a mounting region so that at least two placement object blocks among the plurality of placement object blocks overlap each other to form an overlap region, and an optimization section changing arrangement of the internal components in at least one placement object block among the placement object blocks forming the overlap region while using the overlap region to optimize at least one placement object block.

REFERENCES:
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patent: 2006/0075369 (2006-04-01), Dillon et al.
patent: 2006/0242613 (2006-10-01), Fukazawa
patent: 2008/0134120 (2008-06-01), Wang et al.
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patent: 9-330983 (1997-12-01), None
patent: 2000-20566 (2000-01-01), None
patent: 2003-45780 (2003-02-01), None
International Search Report of PCT/JP2005/011288, date of mailing Sep. 20, 2005.

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