Floorplan visualization method using gate count and gate...

Details Floorplan visualization method using gate count and gate... Floorplan visualization method using gate count and gate...

2007-03-27

2007-03-27

Do, Thuan (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

11012741

ABSTRACT:
A method for floorplan visualization comprising the steps of (A) receiving design information for an integrated circuit design comprising one or more subsystems, (B) generating one or more gate count estimates for the one or more subsystems of the integrated circuit design, (C) generating one or more gate density estimates for gates of the one or more subsystems mapped to one or more programmable areas of a programmable platform device and (D) generating a visual representation of one or more area estimations for each of the one or more subsystems based on the one or more gate count estimates and the one or more gate density estimates.

REFERENCES:
patent: 6968514 (2005-11-01), Cooke et al.

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