Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-06-13
2006-06-13
Whitmore, Stacy A. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
07062743
ABSTRACT:
A method and system for evaluating a floorplan and for defining a global buffered routing for an integrated circuit including constructing a graphical representation of the integrated circuit floorplan, including wire capacity and buffer capacity; formulating an integer linear program from said graphical representation; finding a solution to said integer linear program.
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Albrecht Christoph
Kahng Andrew B.
Mandoiu Ion I.
Zelikovsky Alexander Z.
Greer Burns & Crain Ltd.
Levin Naum
The Regents of the University of California
Whitmore Stacy A.
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