Floor plan tester for integrated circuit design

Details Floor plan tester for integrated circuit design Floor plan tester for integrated circuit design

2002-03-27

2004-03-02

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06701493

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to the design of integrated circuits. More specifically, but without limitation thereto, the present invention relates to methods for testing an integrated circuit design for ramptime violations.
BACKGROUND OF THE INVENTION
The physical design of an integrated circuit chip includes a plurality of cells, or macros, each of which contains one or more circuit elements arranged to perform a specific function. Each of these cells has one or more pins that are connected by wires to one or more pins of other cells in the chip. The set of pins connected by the wire defines a net, and a netlist is a list of all the nets in the chip. Each cell may represent a single circuit element, such as a gate, or a cell may represent several circuit elements interconnected in a standardized manner to perform a specific function. Cells that consist of two or more interconnected gates or other circuit elements may also be made available to a circuit designer in a library of standard cell designs. In a chip design, or chip layout, cells generally have a rectangular outline. Ordinal cells usually have the same height, although they may differ in width.
Ordinal cells are typically arranged in rectangular regions along rows in a chip. The height of each row is equal to the common height of the ordinal cells, and the length of a row is generally equal to the width of the chip.
A physical design of an integrated circuit, or “floor plan”, receives as input a circuit diagram and generates as output a chip layout that implements the circuit diagram.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method of testing a floor plan prior to resynthesis includes attempting to construct a least-penalty path connecting pins of each long distance pin pair in the floor plan to determine whether the floor plan has an unreachable pin; and if the least-penalty path is constructed, then attempting to construct a least-penalty path connecting pins of each long distance pin pair in the floor plan to determine whether the floor plan has a bottleneck.
In another aspect of the present invention, a computer program product includes a medium for embodying a computer program for input to a computer; and a computer program embodied in the medium according to well known programming techniques for causing the computer to perform the following functions: attempting to construct a least-penalty path connecting pins of each long distance pin pair in the floor plan to determine whether the floor plan has an unreachable pin; and if the least-penalty path is constructed, then attempting to construct a least-penalty path connecting pins of each long distance pin pair in the floor plan to determine whether the floor plan has a bottleneck.


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