Floor plan evaluating method, floor plan correcting method,...

Details Floor plan evaluating method, floor plan correcting method,... Floor plan evaluating method, floor plan correcting method,...

2005-05-12

2010-06-01

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

07730439

ABSTRACT:
A floor plan evaluation method by which a floor plan can be quantitatively evaluated. The floor plan evaluation method includes first extracting a plurality of specified elements, which are specified in advance from data on a floor plan which is made automatically by, e.g., a floor planner, second obtaining an individual evaluation value on each of a plurality of individual evaluation items on the basis of the plurality of specified elements extracted in the first step, and third calculating an integrated evaluation value on the floor plan on the basis of a plurality of individual evaluation values obtained in the second step. Then, a plurality of integrated evaluation values obtained by executing the first to third operations for a plurality of floor plans are compared with one another to relatively evaluate the plurality of floor plans.

REFERENCES:
patent: 2006/0117288 (2006-06-01), Katagiri
patent: 9-128414 (1997-05-01), None
patent: 2001-134621 (2001-05-01), None
patent: 2004-13432 (2004-01-01), None
patent: 2004-334565 (2004-11-01), None
Hayakawa, Jiro et al., “VLSI no Floor Plan Saitekika ni Okeru Kai no Hyoka Hoho ni Tsuite”, Journal of the Institute of Science and Engineering, Chuo University, vol. 2002, No. 8, pp. 31-41, Mar. 31, 2003 , Internet <URL:http://www.ise.chuo-u.ac.jp/TISE/pub/journal08>.

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