Floating resurf LDMOSFET and method of manufacturing same

Active solid-state devices (e.g. – transistors – solid-state diode – With means to increase breakdown voltage threshold – With electric field controlling semiconductor layer having a...

Reexamination Certificate

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C257S328000, C257S335000

Reexamination Certificate

active

06882023

ABSTRACT:
A semiconductor component includes a RESURF transistor (100, 200, 300, 400, 500) that includes a first semiconductor region (110, 210, 310, 410, 510) having a first conductivity type and an electrically-floating semiconductor region (115, 215, 315, 415, 515, 545) having a second conductivity type located above the first semiconductor region. The RESURF transistor further includes a second semiconductor region (120, 220, 320, 420, 520) having the first conductivity type located above the electrically-floating semiconductor region, a third semiconductor region (130, 230) having the first conductivity type located above the second semiconductor region, and a fourth semiconductor region (140, 240, 340, 440, 540) having the second conductivity type located above the second semiconductor region. In a particular embodiment, the fourth semiconductor region and the electrically-floating semiconductor region deplete the second semiconductor region when a reverse bias is applied between the third semiconductor region and the fourth semiconductor region.

REFERENCES:
patent: 5146298 (1992-09-01), Eklund
patent: 1 309 011 (2003-07-01), None
patent: WO 9729518 (1997-08-01), None
Zhu, et al., “Implementation of High-Side, High-Voltage RESURF LDMOS in a sub-half Micron Smart Power Technology,” 2001 Int'l Symposium on Power Semiconductor Devices and ICs, Osaka, Japan, pp. 403-406.
Vishnu Khemka, et al., “Experimental and Theoretical Analysis of Energy Capability of RESURF LDMOSFETs and Its Correlation With Static Electrical Safe Operating Area (SOA),”IEEE Transactions on Electron Devices, vol. 49, No. 6, Jun. 2002.
R. Zhu, et al., “Implementation of High-Side, High-Voltage RESURF LDMOS in a sub-half Micron Smart Power Technology,”Proceedings of the ISPSD, Jun. 2001.

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