Electrical computers and digital processing systems: processing – Dynamic instruction dependency checking – monitoring or... – Scoreboarding – reservation station – or aliasing
Reexamination Certificate
2005-12-13
2005-12-13
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Dynamic instruction dependency checking, monitoring or...
Scoreboarding, reservation station, or aliasing
C712S222000
Reexamination Certificate
active
06976153
ABSTRACT:
A floating point unit comprising: 1) an execution pipeline comprising a plurality of execution stages for executing floating point operations in a series of sequential steps; and 2) a try-again reservation station for storing a plurality of instructions to be loaded into the execution pipeline. Detection of a denormal result in the execution pipeline causes the execution pipeline to store the denormal result in a register array associated with the floating point unit and causes the execution pipeline to store a denormal result instruction in the try-again reservation station. The try-again reservation station subsequently re-loads the denormal result instruction into the execution pipeline and the de-normal result instruction retrieves the denormal result from the register array for additional processing.
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Briggs Willard S.
Oliver David S.
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