Floating point unit power reduction via inhibiting register...

Details Floating point unit power reduction via inhibiting register... Floating point unit power reduction via inhibiting register...

2006-08-01

2006-08-01

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Computer power control

C713S323000, C713S340000

Reexamination Certificate

active

07085940

ABSTRACT:
A system and method for reducing the power consumption in a floating point unit of a processor executing an iterative loop of a program by inhibiting floating point register file writes of interim values of the loop from the floating point multiply adder (FPMADD) unit. A plurality of pipeline registers is resident on the processor and holds a portion of an unrolled loop, and once the end of the loop is detected, the last value produced from the loop in the FPMADD unit is written to the floating point registers.

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