Floating point unit pipeline synchronized with processor pipelin

Details Floating point unit pipeline synchronized with processor pipelin Floating point unit pipeline synchronized with processor pipelin

1996-01-31

1999-01-12

Treat, William M.

G06F 938

Patent

active

058600000

ABSTRACT:
An FPU pipeline is synchronized with a CPU pipeline. Synchronization is achieved by having stalls and freezes in any one pipeline cause stalls and freezes in the other pipeline as well. Exceptions are kept precise even for long floating point operations. Precise exceptions are achieved by having a first execution stage of the FPU pipeline generate a busy signal, when a first floating point instruction enters a first execution stage of the FPU pipeline. When a second floating point instruction is decoded by the FPU pipeline before the first floating point instruction has finished executing in the first stage of the FPU pipeline, then both pipelines are stalled.

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