Stress test mode

Details Stress test mode Stress test mode

1993-12-22

1998-11-10

Le, Vu A.

Static information storage and retrieval

Read/write circuit

Testing

365190, 36518911, G11C 700

Patent

active

058354271

ABSTRACT:
Accelerated failure of processing defects in an integrated circuit memory device is brought about by asserting all wordlines of the memory device to enable all passgates for a plurality of memory cells. Then all bitlines are pulled low to pull low all internal nodes of the plurality memory cells. All active devices in the memory device are turned off or limited to linear region operation. This allows a supervoltage to be applied to the wordlines with internal nodes of the memory cells held low by the bitlines, stressing an oxide barrier between memory cells and wordlines without damaging active devices due to the supervoltage.

REFERENCES:
patent: 4685086 (1987-08-01), Tran
patent: 5132929 (1992-07-01), Ochii
patent: 5166608 (1992-11-01), Bowles
patent: 5629943 (1997-05-01), McClure

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