Floating point processor employing counter controlled shifting

Details Floating point processor employing counter controlled shifting Floating point processor employing counter controlled shifting

1989-01-13

1990-07-24

Harkcom, Gary V.

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G06F 738

Patent

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049439413

ABSTRACT:
The floating point processor performs floating point addition or subtraction on a pair of binary arguments, each of which includes an exponent and a mantissa, without requiring a barrel shifter. The processor utilizes a serial arithmetic scheme in which corresponding portions of the arguments are examined sequentially as they are presented thereby to determine which argument is the larger. The exponent of the larger is loaded into a counter. The counter is decremented stepwise and each of the mantissas is shifted, most significant bits first, into an arithmetic circuit which generates carry save form results, starting when the value held by the counter corresponds to the respective exponent. The carry save form results are subsequently normalized and converted to canonical form by propagating the carries.

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Massachusetts Institute of Technology-VLSI Publications VLSI Memo No. 86-344-Oct. 1986, "A High-Performance VLSI Quaternary Serial Multiplier"-William J. Dally.
IEEE Transactions on Computers, vol. c-34, No. 8, Aug. 1985-A Fast Serial-Parallel Binary Multiplier-R. Gnanasekaran.

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