Edward S. Harriman, Jr.

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Apparatus for performing an atomic add instructions

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent

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Distributed pipeline memory architecture for a computer...

Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Least weight routing
Reexamination Certificate

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Floating point processor employing counter controlled shifting

Boots – shoes – and leggings
Patent

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Method and apparatus for handling cache misses in a computer sys

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Method and apparatus for handling cache misses in a computer...

Electrical computers and digital processing systems: multicomput – Computer-to-computer data routing – Least weight routing
Reexamination Certificate

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Profile ID: LFUS-PAI-P-350591

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