Floating point normalization and rounding prediction circuit

Details Floating point normalization and rounding prediction circuit Floating point normalization and rounding prediction circuit

1989-04-17

1990-07-10

Harkcom, Gary V.

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364745, G06F 738

Patent

active

049411209

ABSTRACT:
Apparatus for enhancing certain floating point arithmetic operations, by examining the initial operands and the exponent and fractional results and predicting when the steps of postnormalization and rounding can be skipped. The fraction result format enables a prediction of normalization and rounding under each of the addition, subtraction and multiplication possibilities, and under each of the various choices of rounding mode which are used in floating point arithmetic.

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patent: 4796217 (1989-01-01), Takahashi et al.
Finney et al, "Rounding IEEE Floating Point Results", IBM Tech. Disclosure Bull. vol. 27, No. 5, Oct. 1984, pp. 3138-3140.

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