Floating-point division cell

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364761, 364766, G06F 738, G06F 752

Patent

active

052068269

ABSTRACT:
A floating-point division cell consisting of partial remainder data register for storing parallel-partial-remainder data or third partial remainder data, divisor data register for storing parallel-divisor data or third divisor data, low-order divisor data generator for receiving the low-order portion of the divisor data and generating low-order divisor data, low-order partial remainder calculator for obtaining low-order multi-divisor data by multiplying the low-order divisor data and a multiple of 2 together and calculating new low-order partial remainder data by subtracting or adding the low-order multi-divisor data from/to the low-order portion of the partial remainder data, high-order divisor data generator for receiving the high-order portion of the divisor data and generating high-order divisor data, and high-order partial remainder calculator for obtaining high-order multi-divisor data by multiplying the high-order divisor data and a multiple of 2 together and calculating new high-order partial remainder data by subtracting or adding the high-order multi-divisor data from/to the high-order portion of the partial remainder data.

REFERENCES:
patent: 4722069 (1988-01-01), Ikeda
patent: 4996660 (1991-02-01), Beacom et al.
patent: 5097435 (1992-03-01), Takahashi
patent: 5105378 (1992-04-01), Mori
Hwang Standard Handbook for Electronic Engineers Chap. 7, Sec. 9: 236-240 (Computer No Kousoku Enzan Houshiki), Sep. 1, 1980.

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