Floating-point addition/substraction processing apparatus and me

Details Floating-point addition/substraction processing apparatus and me Floating-point addition/substraction processing apparatus and me

1995-09-19

1997-11-04

Malzahn, David H.

Boots, shoes, and leggings

36471504, G06F 750

Patent

active

056847297

ABSTRACT:
To offer a floating-point addition/subtraction processing apparatus and a method thereof, capable of shortening the computation time, the floating-point calculation processing apparatus includes an approximate shift mount predicting unit for predicting a shift amount for normalization by using the input floating-point data to be addition/subtraction processed within an error of 1 bit, a shift error detecting unit for detecting a difference between the predicted shift amount and a correct shift amount, and an bit shifter for correcting a result, obtained by normalization using the predicted shift amount, by the detected difference of the two shift amounts, wherein a round-off determination and a shift amount calculation are processed in parallel before a normalization shift processing is executed.

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patent: 5343413 (1994-08-01), Inoue
patent: 5373461 (1994-12-01), Bearden et al.
patent: 5568412 (1996-10-01), Han et al.

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