Floating-point adder performing floating-point and integer...

Details Floating-point adder performing floating-point and integer... Floating-point adder performing floating-point and integer...

1999-03-23

2003-03-04

Mai, Tan V. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C708S495000

Reexamination Certificate

active

06529928

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to processors and more particularly to a floating-point adder unit performing floating-point and integer operations within such processors.
BACKGROUND OF THE INVENTION
Digital devices perform a variety of arithmetic operations on binary numerical data. A processor within such digital devices includes a major subdivision called an arithmetic logic unit (ALU). The ALU performs a variety of data processing and arithmetic operations under the control of the processor. The first processors had only one ALU. Modem chips may have several ALUs that commonly are classed into two types. One basic type of ALU is an integer unit which carries out simple integer mathematical operations including add, subtract, multiply, shift and logical instructions. More powerful processors also include a second type of ALU, referred to as a floating-point unit, that handles advanced math operations on numbers with a wider range than simple integers (such as 1.03×10
−19
for example.) Floating-point units use separate, dedicated instructions for their advanced functions.
Devices that process both floating point and integer operations commonly have both a floating-point unit and an integer unit for performing arithmetic operations. However, it is often undesirable to add additional hardware such as a separate integer adder in order to implement the arithmetic operations for integer operands. What is needed is an apparatus for and method of performing arithmetic integer operations without requiring separate integer and floating-point hardware.
SUMMARY DESCRIPTION OF THE DRAWINGS
A floating-point adder unit performing both floating-point operations and integer operations adds functionality without adding substantial additional hardware to the ALU.
One aspect of the floating-point adder unit comprises logic for comparing exponents, logic for selecting and shifting a co-efficient, and logic for adding coefficients. In operation, the floating-point adder unit performs integer addition, subtraction, and compare operations using substantially the same hardware as used for floating-point operations. The output of the logic for comparing exponents represents the most significant bits of the result of the integer operation. The output of the logic for adding coefficients represents the least significant bits of the result of the integer operation. If there is a carry from the logic for adding coefficients, the value of the carry is added to the partial result representing the most significant bits of the integer operation.
The present invention performs both floating-point and integer operations utilizing the floating-point adder. The floating-point adder desirably permits all floating-point and integer add, subtract and compare operations to be performed without adding substantial additional hardware to the ALU for the integer operations. Thus, the floating-point adder permits execution of all floating-point and integer operations utilizing one functional unit.
Still other and further embodiments, aspects and advantages of the invention will become apparent by reference to the drawings and by reading the following detailed description.


REFERENCES:
patent: 5357237 (1994-10-01), Bearden et al.
patent: 5490100 (1996-02-01), Kableshkov
patent: 6148316 (2000-11-01), Herbert et al.

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