Floating gate type non-volatile semiconductor memory device

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257314, 257317, 257320, 257326, H01L 2976, H01L 29788

Patent

active

057510369

ABSTRACT:
A tunnel region is surrounded by an impurity diffusion layer and a drain diffusion layer, and a coupling portion coupling one and the other end portions of a floating gate to each other is arranged on only an isolation region. With this arrangement, even if a parasitic inversion layer is formed below the other end portion upon extraction of electrons, the parasitic inversion layer does not contact a semiconductor substrate, resulting in a small substrate current. Therefore, a high-voltage, large-current external power supply need not be prepared in addition to a normal voltage power supply.

REFERENCES:
patent: 5138410 (1992-08-01), Takebuchi
patent: 5273923 (1993-12-01), Chang et al.

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