Active solid-state devices (e.g. – transistors – solid-state diode – Heterojunction device – Field effect transistor
Reexamination Certificate
2000-06-15
2001-11-06
Munson, Gene M. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Heterojunction device
Field effect transistor
C257S191000, C257S316000, C257S616000
Reexamination Certificate
active
06313486
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to field effect transistors, and more particularly the invention relates to insulated field effect transistors (IGFETS) and metal oxide silicon transistors (MOS) having a floating gate for use in electrically erasable, programmable read-only memory (EEPROM) cells as Flash EEPROM cells.
The MOS transistor has source and drain regions separated by a channel region with the conduction of the channel region controlled by voltage biasing an overlying gate. The Flash EEPROM device has the structure of a metal-oxide-semiconductor field effect transistor (MOSFET) but additionally includes an electrically isolated gate, or floating gate, to store charge. Controlling the amount of charge on the floating gate alters the threshold voltage and creates a nonvolatile memory function. The cell is read in the same manner as a MOSFET. Flash memory development is therefore driven by some of the same concerns as MOS technology, but to the demands for scalable devices with high access times and low leakage currents, it adds the requirement of efficient, controllable gate currents, and channel hot electron (CHE) programming used in conventional flash cells. As the drain and gate voltages are lowered, however, this method becomes less efficient.
Since flash memory is used mostly in mobile applications, low power operation is desirable. For programming with lower drain and gate voltages, a negative substrate voltage may be applied that produces a different programming mechanism that is more effective than CHE programming at these lower voltages. Channel initiated secondary electron (CHISEL) injection occurs when a substrate bias is applied, and the mechanism is also known as substrate current induced hot electron (SCHE) injection. Channel electrons gain energy as they travel to the drain and produce primary impact ionization. The holes generated in the drain then travel back across the drain junction and gain energy as they pass through the depletion region where they can produce secondary impact ionization (SII). the secondary electrons created by SII can travel back to the Si-SiO
2
interface and be injected into the floating gate.
The present invention is directed to a floating gate field effect transistor in which secondary electron injection is enhanced when programming the floating gate.
SUMMARY OF THE INVENTION
In accordance with the invention, a field effect transistor comprises a semiconductor body having source and drain regions formed in spaced surface regions of the semiconductor. A channel region between the source and drain regions includes a compressively strained Si
x
Ge
1−x
alloy layer with a silicon cap layer over the alloy layer. Conduction in the channel region is controlled by a gate structure including a control gate over the channel region and a floating gate between the control gate and the channel region.
The voltage threshold of the transistor is programmed by selectively injecting electrons from the channel region into the floating gate. Lower programming voltages are realized due to increased secondary impact ionization with the presence of the heterostructure interface in the channel and the smaller bandgap of the silicon-germanium layer.
In a preferred embodiment, the Si
x
Ge
1−x
layer is grown on a silicon substrate with a graded mole fraction, 1−x, increasing from 0 to a desired maximum end of growth direction. The maximum value is then maintained during the remainder of the Si
x
Ge
1−x
layer growth, and the whole alloy layer is kept below a critical thickness that maintains pseudomorphic strain. A cap layer of silicon is then epitaxially grown on top of the alloy layer that serves as a channel for the device.
The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawings.
REFERENCES:
patent: 4499557 (1985-02-01), Holmberg et al.
patent: 4599705 (1986-07-01), Holmberg et al.
patent: 4870470 (1989-09-01), Bass, Jr. et al.
patent: 5162880 (1992-11-01), Hazama et al.
patent: 5272365 (1993-12-01), Nakagawa
patent: 5334855 (1994-08-01), Moyer et al.
patent: 5341328 (1994-08-01), Ovshinsky et al.
patent: 5349209 (1994-09-01), Moyer et al.
patent: 5432356 (1995-07-01), Imamura
patent: 5451800 (1995-09-01), Mohammad
patent: 5534712 (1996-07-01), Ovshinksy et al.
patent: 5534713 (1996-07-01), Ismail et al.
patent: 5546340 (1996-08-01), Hu et al.
patent: 5659504 (1997-08-01), Bude et al.
patent: 5698869 (1997-12-01), Yoshimi et al.
patent: 5801396 (1998-09-01), Chan et al.
patent: 5818761 (1998-10-01), Onakado et al.
patent: 5821136 (1998-10-01), Chan et al.
patent: 5821577 (1998-10-01), Crabbe et al.
patent: 5901084 (1999-05-01), Ohnakado
patent: 5926414 (1999-07-01), McDowel et al.
patent: 5986581 (1999-11-01), Magdaleno, II et al.
patent: 5991200 (1999-11-01), Seki et al.
patent: 6013950 (2000-01-01), Nasby
patent: 6031263 (2000-02-01), Forbes et al.
patent: 6207978 (2001-03-01), Fastow
Banerjee Sanjay K.
Kencke David L.
Board of Regents , The University of Texas System
Munson Gene M.
Townsend and Townsend / and Crew LLP
Woodward Henry K.
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