Floating gate or flash EPROM transistor array having contactless

Details Floating gate or flash EPROM transistor array having contactless Floating gate or flash EPROM transistor array having contactless

1994-01-25

1995-03-21

Ngo, Ngan V.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257314, 257315, 257319, 257321, 365185, 365218, 365900, H01L 2968, H01L 2978

Patent

active

053998910

ABSTRACT:
Novel contactless FLASH EPROM cell and array designs, and methods for fabricating the same is based on a unique drain-source-drain configuration, in which a single source diffusion is shared by two columns of transistors. An elongated first drain diffusion region, an elongated source diffusion region, and an elongated second drain diffusion region, are formed in a semi-conductor substrate along essentially parallel lines. Field oxide regions are grown on opposite sides of the first and second drain diffusion regions. Floating gates and control gate wordlines are formed orthogonal to the drain-source-drain structure to establish two columns of storage cells having a shared source region. The shared source region is coupled through a bottom block select transistor to a virtual ground terminal. Each drain diffusion region is coupled through a top block select transistor to global bitline. The cell structure uses two metal global bitlines which extend essentially parallel to the drain, source and drain diffusion regions, and a virtual ground conductor which couples a plurality of columns of transistors to a virtual ground terminal through a horizontal conductor, such as a buried diffusion line.

REFERENCES:
patent: 4258378 (1981-03-01), Wall
patent: 4451904 (1984-05-01), Sugiura et al.
patent: 4639893 (1987-01-01), Eitan
patent: 4698787 (1987-10-01), Mukherjee et al.
patent: 4780424 (1988-10-01), Holler et al.
patent: 4792925 (1988-12-01), Corda et al.
patent: 4812885 (1989-03-01), Riemenschneider
patent: 5012446 (1991-04-01), Bergemont
patent: 5023681 (1991-06-01), Ha
patent: 5023837 (1991-06-01), Schreck et al.
patent: 5028979 (1991-07-01), Mazzali
patent: 5045489 (1991-09-01), Gill et al.
patent: 5060195 (1991-10-01), Gill et al.
patent: 5117269 (1992-05-01), Bellizza et al.
patent: 5168335 (1992-12-01), D'Arrigo et al.
patent: 5245570 (1993-09-01), Fazio et al.
Kazerounian, et al.; "Alternate Metal Virtual Ground EPROM Array Implemented in a 0.8 .mu.M Process for Very High Density Applications"; IEDM, published by IEEE, 1991; pp. 11.5.1 to 11.5.4.
Kodama, et al.; "A Symmetrical Side Wall (SSW)-DSA Cell for a 64 Bit Flash Memory"; IEDM, published by IEEE, 1991; pp. 11-3-1, to 11-3-4.
McConnell, et al.; "An Experimental 4-Mb Flash EPROM with Sector Erase"; IEEE Journal of Solid-State Circuits; vol. 26, No. 4, Apr., 1991; pp. 484-489.
Woo, et al.; "A Novel Memory Cell Using Flash Array Contactless EPROM (Face) Technology"; IEDM, published by IEEE, 1990; pp. 5.1.1-5.1.4.
Woo, et al.; "A Poly-Buffered Face Technology for High Density Flash Memories"; 1991, Symposium on VLSI Technology; pp. 73-74.

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