Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-05-17
2005-05-17
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S314000, C257S315000, C257S316000
Reexamination Certificate
active
06894343
ABSTRACT:
Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion being positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell. Techniques for manufacturing such flash EEPROM split-channel cell arrays are also described.
REFERENCES:
patent: 4811067 (1989-03-01), Fitzgerald et al.
patent: 4835741 (1989-05-01), Baglee
patent: 4890145 (1989-12-01), Malhi
patent: 4975384 (1990-12-01), Baglee
patent: 4990979 (1991-02-01), Otto
patent: 5070032 (1991-12-01), Yuan et al.
patent: 5095344 (1992-03-01), Harari
patent: 5172338 (1992-12-01), Mehrotra et al.
patent: 5313421 (1994-05-01), Guterman et al.
patent: 5315142 (1994-05-01), Acovic et al.
patent: 5315541 (1994-05-01), Harari et al.
patent: 5343063 (1994-08-01), Yuan et al.
patent: 5411905 (1995-05-01), Acovic et al.
patent: 5486714 (1996-01-01), Hong
patent: 5495441 (1996-02-01), Hong
patent: 5498564 (1996-03-01), Geissler et al.
patent: 5576567 (1996-11-01), Mori
patent: 5579259 (1996-11-01), Samachisa et al.
patent: 5606521 (1997-02-01), Kuo et al.
patent: 5616510 (1997-04-01), Wong
patent: 5643814 (1997-07-01), Chung
patent: 5661053 (1997-08-01), Yuan
patent: 5712180 (1998-01-01), Guterman et al.
patent: 5786612 (1998-07-01), Otani et al.
patent: 5891774 (1999-04-01), Ueda et al.
patent: 5949101 (1999-09-01), Aritome
patent: 6037221 (2000-03-01), Lee et al.
patent: 6103573 (2000-08-01), Harari et al.
patent: 6151248 (2000-11-01), Harari et al.
patent: 6222762 (2001-04-01), Guterman et al.
patent: 6281075 (2001-08-01), Yuan et al.
patent: 6316315 (2001-11-01), Hofmann et al.
patent: 6391716 (2002-05-01), Liou
patent: 6512263 (2003-01-01), Yuan et al.
patent: 6532172 (2003-03-01), Harari et al.
patent: 20020118574 (2002-08-01), Gongwer et al.
patent: 0 601 747 (1993-11-01), None
patent: 03-042873 (1995-02-01), None
patent: 10-41414 (1998-02-01), None
patent: 10041414 (1998-02-01), None
patent: 252221 (1995-07-01), None
patent: WO 9732309 (1997-09-01), None
Ogura et al. “Low Voltage, Low Current, High Speed Program step split gate Cell with Ballistic Direct Injection for EEPROM/Flash,”IEEE Publication, Sep. 1998, pp. 36.5.1-36.5.4.
Di-Son Kuo et al. , “TEFET—A High Density, Low Erase Voltage, Trench Flash EEPROM,”IEEE Publication, Apr. 1994, pp. 51-52.
Pein et al. , “Performance of the 3-D Sidewall Flash EPROM Cell,”Symposium on VLSI Technology Digest of Technical Papers(IEEE), Nov. 1993, pp. 2.1.1-2.1.4.
Notification of Transmittal of the International Search Report mailed Jan. 29, 2003.
Harari Eliyahou
Samachisa George
Yuan Jack H.
Flynn Nathan J.
Parsons Hsue & de Runtz LLP
Quinto Kevin
SanDisk Corporation
LandOfFree
Floating gate memory cells utilizing substrate trenches to... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Floating gate memory cells utilizing substrate trenches to..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Floating gate memory cells utilizing substrate trenches to... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3388571