Floating gate memory cell structure with programming...

Details Floating gate memory cell structure with programming... Floating gate memory cell structure with programming...

1998-12-21

2001-05-15

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S320000

Reexamination Certificate

active

06232631

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to nonvolatile memory, and particularly a non-volatile memory structure optimized for particular applications such as programmable logic devices (PLD's).
2. Description of the Related Art
Non-volatile memory devices of the type commonly referred to in the art as EPROM, EEPROM, or Flash EEPROM serve a variety of purposes, and are hence provided in a variety of architectures and circuit structures.
As with many types of integrated circuit devices, some of the main objectives of non-volatile memory device designers are to increase the performance of devices, while decreasing device dimensions and consequently increasing circuit density. Cell designers strive for designs which are reliable, scalable, cost effective to manufacture and able to operate at lower power, in order for manufacturers to compete in the semiconductor industry. EEPROM devices are one such device that must meet these challenges. In some applications, such as flash memory cards, density is at a premium, while in applications such as programmable logic devices (PLD's), reliability and speed are more important and space is at less of a premium.
EEPROMS (electrically erasable/programmable read-only memories) generally employ Fowler-Nordheim (F-N) tunneling for both programming and erasing. The term “flash”, when used with “EEPROM”, generally refers to a device programmed by hot electron injection. Generally, flash technology employs a floating gate structure with a thin oxide layer between the floating gate and the drain side of the transistor where Fowler-Nordheim tunneling occurs.
As process technology progresses toward the so-called 0.18 and 0.13 micron processes, the conventional “stacked gate” EEPROM structure has given way to different cell designs and array architectures, all intended to increase density and reliability in the resulting circuit. In addition, designers are driven to reduce the power requirements of such devices. In non-volatile memory devices, the program and erase functions generally require much larger voltages than the read function requires. Consequently, designers are motivated to reduce programming and erase voltages for nonvolatile memory devices.
In the self-aligned, “stacked gate” cell, a high quality oxide is required, as well as a unique drain and source structure optimized for program and erase operations, respectively, and complementary adaptive program and erase algorithms. Typically, in the stacked gate EEPROM, in order to store a logical zero, electrons are injected onto the floating gate to provide a negative voltage on the floating gate thus increasing the control gate threshold voltage needed to turn on the transistor. Likewise, in order to erase the EEPROM, electrons are removed from the floating gate thereby decreasing the threshold voltage and a logical one is stored on the gate. While stacked gate embodiments have existed and worked well for some time, improved alternative cells have resulted in higher performance integrated circuit devices.
One example of an alternative to the stacked gate EEPROM structure is shown in U.S. Pat. No. 4,924,278, issued to Stewart Logie on May 8, 1990 and assigned to the assignee of the present invention. The EEPROM structure disclosed therein utilizes a single layer of polycrystalline silicon so as to eliminate the need to form a separate control gate and floating gate. The EEPROM structure shown therein is made up of three separate NMOS transistors: a write transistor, a read transistor, and a sense transistor. In order to “program” the floating gate, a net positive charge is placed on the gate by removing free electrons from the floating gate. Likewise, to erase the floating gate, the floating gate is given a net negative charge by injecting electrons onto the floating gate. This convention will be used in the final description of the present invention. This basic EEPROM structure has been well exploited in commercial devices. Nevertheless, as process technologies and practical considerations drive designers toward higher performance, alternative designs are investigated. For example, the aforementioned cell structure requires, in a number of embodiments, a minimum oxide thickness of about 90 Å for the program junction oxide region in order to prevent charge loss due to direct tunneling under to the presence of the high electric field across this region.
An alternative to the aforementioned FN tunneling-based cell structure is presented in Ranaweera, et al., “Performance Limitations of a Flash EEPROM Cell, Programmed With Zener Induced Hot Electrons,” University of Toronto Department of Electrical Engineering (1997). Discussed therein is a flash EEPROM cell which accomplishes programming and erase by establishing a reverse breakdown condition at the drain/substrate junction, generating hot electrons which are then swept onto the floating gate to program the cell.
FIGS. 1A
,
1
B and
1
C of Ranaweera, et al. are reproduced as
FIGS. 1A
,
1
B and
1
C of the present application.
FIGS. 1B and 1C
are cross-sections of the plan view of the cell shown in FIG.
1
A. As shown in
FIG. 1C
, a “ZEEPROM” cell comprises a source and drain region, floating gate and control gate, with a P+ pocket implant extending part way across the width of the drain region to generate hot electrons for programming. The flash ZEEPROM cells are fabricated using CMOS compatible process technology, with the addition of a heavily doped boron implant for the P+ region replacing the LDD region. A sidewall spacer is necessary to form the self-aligned N+ source and drain regions and to avoid counter-doping of the P+ pocket.
To program the flash ZEEPROM cell, the P+ N+ junction is reverse-biased to create an electric field of approximately 10
6
volt/cm. and generate energetic hot electrons independent of the channel length. The P+ region adjacent to the drain enhances this generation. A low junction breakdown voltage can be used for programming by optimizing the P+ N+ junction depth and profiles. One disadvantage of this cell is that a low drain voltage (approximately one volt) must be used to read the cell since the P+ region exhibits a low breakdown voltage which can contribute to “soft programming” due to unwanted charge injection to the gate (generally referred to herein as “program disturb”). Erasing in the cell described by Ranaweera is performed by Fowler-Nordheim tunneling of electrons from the floating gate to the source region using a negative gate voltage and positive supply voltage connected to the source similar to conventional flash EEPROM cells.
Another alternative cell structure using hot election programming generated by a reverse breakdown condition at the drain is described in the context of a method for bulk charging and discharging of an array of flash EEPROM memory cells in U.S. Pat. No. 5,491,657 issued to Haddad, et al., assigned to the assignee of the present invention. In Haddad, et al., a cell structure similar to that shown in cross-section in
FIG. 1
B of the present application may be used, as well as a substrate-biased p-well in n-well embodiment. In the first embodiment, an N+ source region includes an N+ implant region and an N diffusion region, and the erase (in this case removing electrons) operation is accomplished by applying (−)8.5 volts to the control gate for 100 milliseconds, and (+)5 volts to the source for 100 milliseconds, with the drain being allowed to float. In contrast, programming (in this case adding electrons to the gate) is achieved by applying a negative 8.5 volt to the substrate for 5 microseconds, zero volts to the drain and control gate with the source floating. The bulk charging operation can just as easily be done on the source side rather than the drain side in a case where the cell is provided in a P well by applying −8.5 volts to the P well for 5 microseconds, 0 volts to the source and control gate with the drain being allowed to float.
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