Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-10-25
2005-10-25
Le, Dung A. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S328000, C438S270000
Reexamination Certificate
active
06958513
ABSTRACT:
A method of forming an array of floating gate memory cells, and an array formed thereby, wherein each memory cell includes an electrical conductive floating gate formed in a trench in a semiconductor substrate, and an electrical conductive control gate having a portion disposed over and insulated from the floating gate. An electrical conductive tunneling gate is disposed over and insulated from the control gate by an insulating layer to form a tri-layer structure permitting both electron and hole charges tunneling through at similar tunneling rate. Spaced apart source and drain regions are formed with the source region disposed adjacent to and insulated from a lower portion of the floating gate, and with the drain region disposed adjacent to and insulated from an upper portion of the floating gate with a channel region formed therebetween and along a sidewall of the trench.
REFERENCES:
patent: 4957877 (1990-09-01), Tam et al.
patent: 5146426 (1992-09-01), Mukherjee et al.
patent: 5432739 (1995-07-01), Pein
patent: 5563083 (1996-10-01), Pein
patent: 5780341 (1998-07-01), Ogura
patent: 6372617 (2002-04-01), Kitamura
patent: 6479863 (2002-11-01), Caywood
patent: 6621107 (2003-09-01), Blanchard et al.
patent: 2004/0021170 (2004-02-01), Caywood
Kitamura T. et al., “A Low Voltage Operating Flash Cell with High Coupling Ratio Using Horned Floating gate with Fine HSG”, Symposium on VLSI Tech Digest, p. 104, 1998.
Lai, “Flash Memories: Where We Were and Where We Are Going”, IEDM Technical Digest, pp. 971-973, 1998.
Kuo et al., “TEFET—A High Density, Low Erase Voltage, Trench Flash EEPROM”, Symposium on VLSI Tech Digest, p. 51, 1994.
H. Pein et al, “Performance of the 3-D Sidewall Flash EPROM Cell”, IEDM Tehnical Digest, pp. 11-14, 1993.
LandOfFree
Floating-gate memory cell having trench structure with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Floating-gate memory cell having trench structure with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Floating-gate memory cell having trench structure with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3443562