Floating-gate memory cell and memory device and electronic...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S315000, C257SE29300, C438S429000

Reexamination Certificate

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07898017

ABSTRACT:
A floating-gate memory cell has a tunnel dielectric layer that overlies a silicon-containing semiconductor substrate and that is adjacent a trench formed in the semiconductor substrate. A floating-gate layer, having at least one silicon-containing layer, overlies the tunnel dielectric layer. An intergate dielectric layer overlies the floating-gate layer, and a control gate layer overlies the intergate dielectric layer. A first silicon oxide layer is formed on an edge of the at least one silicon-containing layer of the floating-gate layer and extends across a first portion of an edge of the tunnel dielectric layer. A second silicon oxide layer is formed on a sidewall of the trench and extends across a second portion of the edge of the tunnel dielectric layer.

REFERENCES:
patent: 5250461 (1993-10-01), Sparks
patent: 5641694 (1997-06-01), Kenney
patent: 6180486 (2001-01-01), Leobandung
patent: 6545297 (2003-04-01), Noble, Jr.
patent: 6631086 (2003-10-01), Bill et al.
patent: 6635543 (2003-10-01), Furukawa
patent: 2005/0009295 (2005-01-01), Chan
patent: 2002001021 (2002-01-01), None

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