Floating gate memory cell and device

Static information storage and retrieval – Magnetic bubbles – Guide structure

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Details

357 55, 365185, H01L 2968, H01L 2906, G11C 1134

Patent

active

049790048

ABSTRACT:
One embodiment of the invention provides an EPROM and a method of fabricating an EPROM with enhanced capacitive coupling. Trenched memory cells each comprise a pleat-shaped floating gate with the control gate nested in a fold of the floating gate to increase the coupling ratio with the control gate. As a result higher programming speed and improved cell density may be obtained for a given programming voltage. Formation of bit lines along trench walls results in lower bit line resistivity for a given cell density.

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IBM Technical Disclosure Bulletin, vol. 24, #3, pp. 1331-1333, by Tsang.
Agerico L. Esquivel et al., "A Novel Trench-Isolated Buried N+ Famos Transistor Suitable for High Density EPROM's", IEEE vol. 8, No. 4, Apr. 87, pp. 146-147.

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