Floating gate FPGA cell with counter-doped select device

Details Floating gate FPGA cell with counter-doped select device Floating gate FPGA cell with counter-doped select device

1996-08-09

1999-04-13

Crane, Sara

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257319, 257321, H01L 29788

Patent

active

058941487

ABSTRACT:
The present invention provides for an improved EPROM transistor cell which forms the programming portion of the programmable interconnect interconnect of an FPGA integrated circuit, and a method of manufacturing the EPROM cell. The EPROM cell has a floating gate disposed over a P region of the substrate. Aligned with one edge of the floating gate and at the surface of the substrate is a lightly doped P- region; on the opposite edge of the floating gate is a heavily doped N+ region. A control gate lies over the P-, P substrate and over the N+ region. N+ regions are formed at the opposite edges of the control gate. One N+ region is contiguous to the P- region and forms the source of the EPROM cell and the other N+ region is connected to the N+ region under the control gate and forms the drain of the EPROM cell. This structure allows for easy process control of the V.sub.T of the access transistor formed by the control gate and the P- surface, and of the space charge region formed by the P substrate and the N+ drain of the EPROM cell.

REFERENCES:
patent: 4302766 (1981-11-01), Guterman et al.
patent: 4317273 (1982-03-01), Guterman et al.
patent: 4435790 (1984-03-01), Tickle et al.
patent: 5293328 (1994-03-01), Amin et al.
patent: 5633518 (1997-05-01), Broze

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