Floating CMOS input circuit that does not draw DC current

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Input noise margin enhancement

Reexamination Certificate

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Details

C326S027000, C326S083000

Reexamination Certificate

active

11205967

ABSTRACT:
A floating CMOS input circuit is disclosed that does not draw direct current. The floating CMOS input circuit comprises a first inverter circuit that is capable of being coupled to an input voltage (Vin) and an n-channel pull-down transistor (N1) that is coupled to the first inverter circuit. The n-channel pull-down transistor (N1) pulls the input voltage (Vin) on the first inverter circuit to a hard ground when the input voltage (Vin) is not driven high. This eliminates the leakage of direct current in the first inverter circuit. The floating CMOS input circuit also powers up in a known state.

REFERENCES:
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patent: 5329174 (1994-07-01), Chiang
patent: 6055191 (2000-04-01), Sher et al.
patent: 6225838 (2001-05-01), Lee
patent: 6265931 (2001-07-01), Lutley et al.
patent: 6859084 (2005-02-01), Stansfield et al.
“Implications of Slow or Floating CMOS Inputs”, Texas Instruments, Feb. 1998, 16 pages.
“The Behaviour of Integrated Bus Hold Circuits” IC24 Data Handbook, Philips Semiconductors, Mar. 1996, 6 pages.

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