Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Input noise margin enhancement
Reexamination Certificate
2008-04-22
2008-04-22
Le, Don (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Input noise margin enhancement
C326S027000, C326S083000
Reexamination Certificate
active
07362126
ABSTRACT:
A floating CMOS input circuit is disclosed that does not draw direct current. The floating CMOS input circuit comprises a first inverter circuit that is capable of being coupled to an input voltage (Vin) and an n-channel pull-down transistor (N1) that is coupled to the first inverter circuit. The n-channel pull-down transistor (N1) pulls the input voltage (Vin) on the first inverter circuit to a hard ground when the input voltage (Vin) is not driven high. This eliminates the leakage of direct current in the first inverter circuit. The floating CMOS input circuit also powers up in a known state.
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Le Don
National Semiconductor Corporation
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